
DS3510
I2C Gamma and VCOM Buffer with EEPROM
_______________________________________________________________________________________
9
Block Diagram
LATCH B
LATCH A
MUX
8-BIT
DAC
0
1
MODE1 BIT
0
1
MODE0 BIT
LD
GHM
GHH
8 BITS
GM10 BANK A
GM10 BANK B
GM10 BANK C
GM10 BANK D
S0/S1 PINS
S0/S1 BITS
I2C
COMP
BANKS
GM10
GHH
GHM
GLM
GLL
GHM
LATCH B
LATCH A
MUX
8-BIT
DAC
0
1
MODE1 BIT
0
1
MODE0 BIT
LD
GHM
GHH
8 BITS
GM6 BANK A
GM6 BANK B
GM6 BANK C
GM6 BANK D
S0/S1 PINS
S0/S1 BITS
I2C
COMP
BANKS
GM6
LATCH B
LATCH A
MUX
8-BIT
DAC
0
1
MODE1 BIT
0
1
MODE0 BIT
LD
GLL
GLM
8 BITS
GM5 BANK A
GM5 BANK B
GM5 BANK C
GM5 BANK D
S0/S1 PINS
S0/S1 BITS
I2C
COMP
BANKS
GM5
GLM
GLL
LATCH B
LATCH A
MUX
8-BIT
DAC
0
1
MODE1 BIT
0
1
MODE0 BIT
LD
GLL
GLM
8 BITS
GM1 BANK A
GM1 BANK B
GM1 BANK C
GM1 BANK D
S0/S1 PINS
S0/S1 BITS
I2C
COMP
BANKS
GM1
LATCH B
LATCH A
MUX
8-BIT
DAC
0
1
MODE1 BIT
0
1
MODE0 BIT
LD
VRL
VRH
8 BITS
VCOM BANK A
VCOM BANK B
VCOM BANK C
VCOM BANK D
S0/S1 PINS
S0/S1 BITS
I2C
COMP
BANKS
VCOM
LOGIC
AND
CONTROL
MODE0 BIT (CR.0)
I2C
INTERFACE
I2C
COMPENSATION
COMP
MODE1 BIT (CR.1)
S0/S1 PINS
S0/S1 BITS (SOFT S0/S1)
LD
SDA
SCL
A0
S0
S1
LD
VCAP
VDD
VCC
GND
DS3510