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參數(shù)資料
| 型號： | DS34C87TN/NOPB |
| 廠商： | National Semiconductor |
| 文件頁數(shù)： | 9/14頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC LINE DRIVER QUAD CMOS 16-DIP |
| 標準包裝： | 25 |
| 類型： | 驅(qū)動器 |
| 驅(qū)動器/接收器數(shù)： | 4/0 |
| 規(guī)程： | RS422 |
| 電源電壓： | 4.5 V ~ 5.5 V |
| 安裝類型： | 通孔 |
| 封裝/外殼： | 16-DIP（0.300"，7.62mm） |
| 供應商設備封裝： | 16-DIP |
| 包裝： | 管件 |
| 其它名稱： | *DS34C87TN *DS34C87TN/NOPB DS34C87TN |
SNLS376B – MAY 1998 – REVISED APRIL 2013
Switching Characteristics
(1)
Parameter
Test Conditions
Min
Typ
Max
Units
tPLH, tPHL
Propagation Delay Input to Output
S1 Open
6
11
ns
Skew
See(2)
S1 Open
0.5
3
ns
tTLH, tTHL
Differential Output Rise And Fall Times
S1 Open
6
10
ns
tPZH
Output Enable Time
S1 Closed
12
25
ns
tPZL
Output Enable Time
S1 Closed
13
26
ns
tPHZ
Output Disable Time(3)
S1 Closed
4
8
ns
tPLZ
Output Disable Time(3)
S1 Closed
6
12
ns
CPD
Power Dissipation Capacitance(4)
100
pF
CIN
Input Capacitance
6
pF
(1)
Unless otherwise specified, min/max limits apply across the
40°C to 85°C temperature range. All typicals are given for VCC = 5V and
TA = 25°C.
(2)
Skew is defined as the difference in propagation delays between complementary outputs at the 50% point.
(3)
Output disable time is the delay from the control input being switched to the output transistors turning off. The actual disable times are
less than indicated due to the delay added by the RC time constant of the load.
(4)
CPD determines the no load dynamic power consumption, PD = CPD V
2CC f + I
CC VCC, and the no load dynamic current consumption, IS
= CPD VCC f + ICC.
Comparison Table of Switching Characteristics into “LS-Type” Load
(1)
VCC = 5V, TA = +25°C, tr ≤ 6 ns, tf ≤ 6 ns (Figure 6, Figure 7, Figure 8, Figure 9, Figure 10, Figure 11)
DS34C87
DS3487
Parameter
Test Conditions
Units
Typ
Max
Typ
Max
tPLH, tPHL
Propagation Delay
6
10
15
ns
Input to Output
Skew
See(2)
1.5
2.0
ns
tTHL, tTLH
Differential Output Rise
4
7
10
15
ns
and Fall Times
tPHZ
Output Disable Time
CL = 50 pF, RL = 200Ω,
8
11
17
25
ns
See(3)
S1 Closed, S2 Closed
tPLZ
Output Disable Time
CL = 50 pF, RL = 200Ω,
7
10
15
25
ns
See(3)
S1 Closed, S2 Closed
tPZH
Output Enable Time
CL = 50 pF, RL = ∞,
11
19
11
25
ns
S1 Open, S2 Closed
tPZL
Output Enable Time
CL = 50 pF, RL = 200Ω,
14
21
15
25
ns
S1 Closed, S2 Open
(1)
This table is provided for comparison purposes only. The values in this table for the DS34C87 reflect the performance of the device but
are not tested or ensured.
(2)
Skew is defined as the difference in propagation delays between complementary outputs at the 50% point.
(3)
Output disable time is the delay from the control input being switched to the output transistors turning off. The actual disable times are
less than indicated due to the delay added by the RC time constant of the load.
4
Copyright 1998–2013, Texas Instruments Incorporated
Product Folder Links: DS34C87T
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