參數(shù)資料
型號： DS33ZH11+
廠商： Maxim Integrated Products
文件頁數(shù)： 98/172頁
文件大?。?/td> 0K
描述： IC MAPPER ETHERNET 100CSBGA
產(chǎn)品培訓模塊： Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標準包裝： 7
應用： 數(shù)據(jù)傳輸
接口： 串行
電源電壓： 1.8V，2.5V，3.3V
封裝/外殼： 100-LFBGA，CSPBGA
供應商設備封裝： 100-CSBGA（10x10）
包裝： 托盤
安裝類型： 表面貼裝
DS33Z11 Ethernet Mapper
31 of 172
8.3 CLOCK STRUCTURE
The DS33Z11 clocks sources and functions are as follows:
Serial Transmit Data (TCLKI) and Serial Receive Data (RCLKI) clock inputs are used to transfer data
from the serial interface. These clocks can be continuous or gapped.
System Clock (SYSCLKI) input. Used for internal operation. This clock input cannot be a gapped clock. A
clock supply with ±100 ppm frequency accuracy is suggested. A buffered version of this clock is provided
on the SDCLKO pin for the operation of the SDRAM. A divided and buffered version of this clock is
provided on the SPICK pin for Serial EEPROM operation. A divided and buffered version of this clock is
provided on REF_CLKO for the RMII/MII interface.
Packet Interface Reference clock (REF_CLK) input that can be 25 or 50 MHz. This clock is used as the
timing reference for the RMII/MII interface.
The Transmit and Receive clocks for the MII Interface (TX_CLK and RX_CLK). In DTE mode, these are
input pins and accept clocks provided by an Ethernet PHY. In the DCE mode, these are output pins and
will output an internally generated clock to the Ethernet PHY. The output clocks are generated by internal
division of REF_CLK. In RMII mode, only the REF_CLK input is used.
REF_CLKO is an output clock that is generated by dividing the 100 MHz System clock (SYSCLKI) by 2 or
4.
A Management Data Clock (MDC) output is derived from SYSCLKI and is used for information transfer
between the internal Ethernet MAC and external PHY. The MDC clock frequency is 1.67 MHz.
The following table provides the different clocking options for the Ethernet interface.
Table 8-1 Clocking Options for the Ethernet Interface
RMIIMIIS
Pin
Speed
DCE/
DTE
REF_CLKO
Output
REF_CLK
Input
RX_CLK
TX_CLK
MDC
Output
0 (MII)
10
Mbps
DTE
25 MHz
+/- 100 ppm
Input from
PHY
Input from
PHY
1.67 MHz
0 (MII)
10
Mbps
DCE
25 MHz
+/- 100 ppm
2.5 MHz
(Output)
2.5 MHz
(Output)
1.67 MHz
0 (MII)
100
Mbps
DCE
25 MHz
+/- 100 ppm
25 MHz
(Output)
25 MHz
(Output)
1.67 MHz
1 (RMII)
10
Mbps
-
50 MHz
+/- 100 ppm
Not Applicable
1.67 MHz
1 (RMII)
100
Mbps
-
50 MHz
+/- 100 ppm
Not Applicable
1.67 MHz
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