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參數(shù)資料
| 型號(hào)： | DS33R11+CJ2 |
| 廠商： | Maxim Integrated Products |
| 文件頁(yè)數(shù)： | 334/344頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC ETH TXRX T1/E1/J1 256-BGA |
| 產(chǎn)品培訓(xùn)模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標(biāo)準(zhǔn)包裝： | 90 |
| 類型： | 收發(fā)器 |
| 規(guī)程： | T1/E1/J1 |
| 電源電壓： | 1.8V, 3.3V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 256-BBGA |
| 供應(yīng)商設(shè)備封裝： | 256-BGA（27x27） |
| 包裝： | 托盤 |
| 其它名稱： | 90-33R11+C01 |
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DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver
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1 DESCRIPTION
The DS33R11 provides interconnection and mapping functionality between Ethernet Packet Systems and T1/E1/J1
WAN Time-Division Multiplexed (TDM) systems. The device is composed of a 10/100 Ethernet MAC, Packet
Arbiter, Committed Information Rate Controller (CIR), HDLC/X.86 (LAPS) Mapper, SDRAM interface, control ports,
Bit Error Rate Tester (BERT), and integrated T1/E1/J1 Transceiver. The packet interface consists of a MII/RMII
Ethernet PHY interface. The Ethernet interface can be configured for 10Mbit/s or 100Mbit/s service. The DS33R11
encapsulates Ethernet traffic with HDLC or X.86 (LAPS) encoding to be transmitted over a T1, E1, or J1 line. The
T1/E1/J1 interface also receives encapsulated Ethernet packets and transmits the extracted packets over the
Ethernet ports. Access is provided to the signals between the Serial port and the integrated T1/E1/J1 Transceiver.
The device includes a software-selectable T1, E1, or J1 single-chip transceiver (SCT) for short-haul and long-haul
applications. The transceiver is composed of an LIU, framer, and two additional HDLC controllers. The transceiver
is software compatible with the DS2155 and DS2156.
The LIU is composed of transmit and receive interfaces and a jitter attenuator. The transmit interface is responsible
for generating the necessary waveshapes for driving the network and providing the correct source impedance
depending on the type of media used. T1 waveform generation includes DSX-1 line build-outs as well as CSU line
build-outs of -7.5dB, -15dB, and -22.5dB. E1 waveform generation includes G.703 waveshapes for both 75
Ω coax
and 120
Ω twisted cables. The receive interface provides network termination and recovers clock and data from the
network. The receive sensitivity adjusts automatically to the incoming signal and can be programmed for 0 to 43dB
or 0 to 12dB for E1 applications and 0 to 30dB or 0 to 36dB for T1 applications. The jitter attenuator removes
phase jitter from the transmitted or received signal. The crystal-less jitter attenuator requires only a 2.048MHz
MCLK for both E1 and T1 applications (with the option of using a 1.544MHz MCLK in T1 applications) and can be
placed in either transmit or receive data paths. An additional feature of the LIU is a CMI coder/decoder for
interfacing to optical networks.
On the transmit side, clock, data, and frame-sync signals are provided to the framer by the backplane interface
section. The framer inserts the appropriate synchronization framing patterns, alarm information, calculates and
inserts the CRC codes, and provides the B8ZS/HDB3 (zero code suppression) and AMI line coding. The receive-
side framer decodes AMI, B8ZS, and HDB3 line coding, synchronizes to the data stream, reports alarm
information, counts framing/coding/CRC errors, and provides clock/data and frame-sync signals to the backplane
interface section. Diagnostic capabilities include loopbacks, PRBS pattern generation/detection, and 16-bit loop-up
and loop-down code generation and detection.
Both the transmit and receive path have two HDLC controllers. The HDLC controllers transmit and receive data
through the framer block. The HDLC controllers can be assigned to any time slot, group of time slots, portion of a
time slot or to FDL (T1) or Sa bits (E1). Each controller has 128-byte FIFOs, thus reducing the amount of
processor overhead required to manage the flow of data. In addition, built-in support for reducing the processor
time is required in SS7 applications.
The backplane interface provides a versatile method of sending and receiving data from the host system. Elastic
stores provide a method for interfacing to asynchronous systems, converting from a T1/E1 network to a 2.048MHz,
4.096MHz, 8.192MHz, or N x 64kHz system backplane. The elastic stores also manage slip conditions
(asynchronous interface).
An 8-bit parallel microcontroller port provides access for control and configuration of all the features of the device.
The internal 100MHz SDRAM controller interfaces to a 32-bit wide 128Mb SDRAM. The SDRAM is used to buffer
the data from the Ethernet and WAN ports for transport. The external SDRAM can accommodate up to 8192
frames with a maximum frame size of 2016 bytes. Diagnostic capabilities include SDRAM BIST, loopbacks, PRBS
pattern generation/detection, and 16-bit loop-up and loop-down code generation and detection. The DS33R11
operates with a 1.8V core supply and 3.3V I/O supply.
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|---|---|
| DS33R11DK | 功能描述:以太網(wǎng)開(kāi)發(fā)工具 DS33R11 Dev Kit RoHS:否 制造商:Micrel 產(chǎn)品:Evaluation Boards 類型:Ethernet Transceivers 工具用于評(píng)估:KSZ8873RLL 接口類型:RMII 工作電源電壓: |
| DS33R41 | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC Inv-Mult Enet Mapper w/Quad T1/E1/J1 Trx RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| DS33R41+ | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC Inv-Mult Enet Mapper w/Quad T1/E1/J1 Trx RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| DS33W11+ | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC Ethernet Over PDH Mapping Devices RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
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