- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄9752 > DS3253N# (Maxim Integrated Products)IC LIU DS3/E3/STS-1 144-CSBGA PDF資料下載
參數(shù)資料
| 型號： | DS3253N# |
| 廠商： | Maxim Integrated Products |
| 文件頁數(shù)： | 26/71頁 |
| 文件大小： | 0K |
| 描述： | IC LIU DS3/E3/STS-1 144-CSBGA |
| 產(chǎn)品培訓模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標準包裝： | 160 |
| 類型： | 線路接口裝置（LIU） |
| 驅(qū)動器/接收器數(shù)： | 3/3 |
| 規(guī)程： | IEEE 1149.1 |
| 電源電壓： | 3.135 V ~ 3.465 V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 144-BGA，CSPBGA |
| 供應商設備封裝： | 144-TECSBGA（13x13） |
| 包裝： | 管件 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁當前第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁
DS3251/DS3252/DS3253/DS3254
32 of 71
10.
JITTER ATTENUATOR
Each LIU contains an on-board jitter attenuator that can be placed in the receive path or the transmit path or can
be disabled. The TJA and RJA pins (hardware mode) or the TCR:TJA and RCR:RJA control bits (CPU bus mode)
specify how the jitter attenuator is used. Setting TJA = RJA = 0 disables the jitter attenuator. To use the jitter
attenuator in the receive path, set RJA = 1 (with TJA = 0). To use it in the transmit path, set TJA = 1. Figure 10-1
shows the minimum jitter attenuation for the device when the jitter attenuator is enabled. Figure 10-1 also shows
the receive jitter transfer when the jitter attenuator is disabled.
The jitter attenuator consists of a narrowband PLL to retime the selected clock, a FIFO to buffer the associated
data while the clock is being retimed, and logic to prevent FIFO over/underflow in the presence of very large jitter
amplitudes. In hardware mode, only 16-bit and 32-bit FIFO depths are available. See Table 6-I. In CPU bus mode,
control bits TCR:JAL[1:0] set the FIFO depth to 16, 32, 64, or 128 bits.
The jitter attenuator requires a transmission-quality master clock (i.e.,
±20ppm frequency accuracy and low jitter).
When enabled in the receive path, the JA can obtain its master clock from the appropriate MCLK pin, from the
clock adapter block, or from the TCLK pin. When enabled in the transmit path, the JA can take its master clock
from the MCLK pin or from the clock adapter block, but not from the TCLK pin. The CDR block also uses the
selected master clock. See Section 12 for more information about master clocks and clock selection.
The JA has a loop bandwidth of master_clock
÷ 2,058,874 (see corner frequencies in Figure 10-1). The JA
attenuates jitter at frequencies higher than the loop bandwidth, while allowing jitter (and wander) at lower
frequencies to pass through relatively unaffected.
In CPU bus mode the jitter attenuator indicates the fill status of its FIFO buffer in the JAFL (JA full) and JAEL (JA
empty) status bits in the SRL register. The JA sets the JAFL bit to indicate that its buffer is full. When the buffer
becomes full, the JA momentarily increases the frequency of the read clock by 6250 ppm to avoid buffer overflow
and consequent data loss. In a similar manner, the JA sets the JAEL bit to indicate that its buffer is empty. When
the buffer becomes empty, the JA momentarily decreases the frequency of the read clock by 6250 ppm to avoid
buffer underflow and consequent data errors. During these momentary frequency adjustments, jitter is passed
through the JA to avoid over/underflow. If the phase noise or frequency offset of the write clock is large enough to
cause the buffer to overflow or underflow, the JA sets both the JAFL bit and the JAEL bit to indicate that data errors
have occurred.
相關PDF資料 |
PDF描述 |
|---|---|
| VI-25H-IU-F3 | CONVERTER MOD DC/DC 52V 200W |
| DS26528G+ | IC TXRX T1/E1/J1 OCT 256-CSBGA |
| DS26324GNA3+ | IC LIU E1/T1/J1 3.3V 256-CSBGA |
| MAX1070CTC+ | IC ADC 10BIT 1.5MSPS 12-TQFN |
| DS21458N+ | IC LIU QUAD T1/E1/J1 256-CSBGA |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| DS3253N# | 功能描述:網(wǎng)絡控制器與處理器 IC Triple DS3/E3/STS-1 Line Interface Unit RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| DS3253N+ | 功能描述:網(wǎng)絡控制器與處理器 IC Triple DS3/E3/STS-1 Line Interface Unit RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| DS3253NA3 | 制造商:Maxim Integrated Products 功能描述:DS3253 REV A3 - Rail/Tube |
| DS3254 | 功能描述:網(wǎng)絡控制器與處理器 IC Quad DS3/E3/STS-1 Line Interface Unit RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| DS3254+ | 功能描述:網(wǎng)絡控制器與處理器 IC Quad DS3/E3/STS-1 Line Interface Unit RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
發(fā)布緊急采購，3分鐘左右您將得到回復。