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| 型號(hào)： | DS3184N |
| 廠(chǎng)商： | Maxim Integrated Products |
| 文件頁(yè)數(shù)： | 42/400頁(yè) |
| 文件大小： | 0K |
| 描述： | IC QUAD ATM/PACKET PHY 400-PBGA |
| 產(chǎn)品培訓(xùn)模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 類(lèi)型： | 調(diào)幀器 |
| 應(yīng)用： | 數(shù)據(jù)傳輸 |
| 安裝類(lèi)型： | 表面貼裝 |
| 封裝/外殼： | 400-BBGA |
| 供應(yīng)商設(shè)備封裝： | 400-PBGA（27x27） |
| 包裝： | 管件 |
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DS3181/DS3182/DS3183/DS3184
136
Figure 10-24. Byte Reordered Packet Format in 16-Bit Mode
Bit 15
Bit 0
Byte 2
Byte 1
1
st Transfer
Byte 4
Byte 3
2
nd Transfer
Byte 2n-2
Byte 2n-3
(n-1)
th Transfer
Byte 2n
Byte 2n-1
n
th Transfer
10.6.6.4 UTOPIA Level 2, Transmit Side
In UTOPIA Level 2, an ATM layer device pushes cells across the system interface. The ATM layer device polls the
individual ports of the DS318x to determine which ports have space available for a cell, and selects a port for cell
transfer. More than one PHY layer device can be present on a UTOPIA Level 2 bus. Whether or not the HEC byte
is transferred with the cells is programmable.
The Transmit System Interface Bus Controller accepts a transmit clock (TSCLK), transmit address (TADR[4:0]),
transmit enable (
TEN), and a transmit data bus consisting of transmit data (TDATA[31:0]), transmit parity (TPRTY),
and transmit start of cell (TSOX). It outputs transmit direct cell available (TDXA) and transmit polled cell available
(TPXA) signals. The transmit data bus is used to transfer cell data whenever one of the ports is selected for cell
data transfer. TSOX is asserted during the first transfer of a cell, cell data is transferred on TDATA, and the data
bus parity is indicated on TPRTY. All signals are sampled or updated using TSCLK. The TDXA and TPXA signals
are used to indicate when the Transmit FIFO has space available for a programmable number of cells. There is a
TDXA for each port in the device. TDXA goes high when the associated port's Transmit FIFO has more space
available than a programmable number of cells. TDXA goes low when the associated port's Transmit FIFO is full
(does not have space for another cell). TPXA reflects the current status of a port's TDXA signal when the port is
polled. The TPXA signal is tri-stated unless one of the ports is being polled for FIFO fill status.
10.6.6.5 UTOPIA Level 3, Transmit Side
In UTOPIA Level 3, the ATM layer device pushes cells across the system interface. The ATM layer device polls the
individual ports of the DS318x to determine which ports have space available for a cell, and selects a port for cell
transfer. Only one PHY layer device can be present on a UTOPIA Level 3 bus. Whether or not the HEC byte is
transferred with the cells is programmable.
The Transmit System Interface Bus Controller accepts a transmit clock (TSCLK), transmit address (TADR[7:0]),
transmit enable (
TEN), and a transmit data bus consisting of transmit data (TDATA[31:0]), transmit parity (TPRTY),
and transmit start of cell (TSOX). It outputs transmit direct cell available (TDXA) and transmit polled cell available
(TPXA) signals. The transmit data bus is used to transfer cell data whenever one of the ports is selected for cell
data transfer. TSOX is asserted during the first transfer of a cell, cell data is transferred on TDATA, and the data
bus parity is indicated on TPRTY. All signals are sampled or updated using TSCLK. The TDXA and TPXA signals
are used to indicate when the Transmit FIFO has space available for a programmable number of cells.
There is a TDXA for each port in the device. TDXA goes high when the associated port's Transmit FIFO has more
space available than a programmable number of cells. TDXA goes low when the associated port's Transmit FIFO
is full (does not have space for another cell). TPXA reflects the current status of a port's TDXA signal when the port
is polled. The TPXA signal is always driven.
10.6.6.6 UTOPIA Level 2, Receive Side
In UTOPIA Level 2, the ATM layer device pulls cells across the system interface. The ATM layer device polls the
individual ports to determine which ports have cells available, and selects a port for cell transfer. More than one
PHY layer device can be present on a UTOPIA Level 2 bus. Whether or not the HEC byte is transferred with the
cells is programmable.
The Receive System Interface Bus Controller accepts a receive clock (RSCLK), receive address (RADR[4:0]), and
receive enable (
REN). It outputs a receive data bus consisting of receive data (RDATA[31:0]), receive parity
(RPRTY), and receive start of cell (RSOX), as well as, receive direct cell available (RDXA) and receive polled cell
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| DS3184N+ | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC Quad ATM/Packet PHYs w/Built-In LIU RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| DS318PIN | 制造商:未知廠(chǎng)家 制造商全稱(chēng):未知廠(chǎng)家 功能描述:Industrial Control IC |
| DS-318PIN | 制造商:MA-COM 制造商全稱(chēng):M/A-COM Technology Solutions, Inc. 功能描述:Plug-In Two-Way Power Divider, 5 - 500 MHz |
| DS-318-PIN | 功能描述:信號(hào)調(diào)節(jié) RoHS:否 制造商:EPCOS 產(chǎn)品:Duplexers 頻率:782 MHz, 751 MHz 頻率范圍: 電壓額定值: 帶寬: 阻抗:50 Ohms 端接類(lèi)型:SMD/SMT 封裝 / 箱體:2.5 mm x 2 mm 工作溫度范圍:- 30 C to + 85 C 封裝:Reel |
| DS319 | 制造商:未知廠(chǎng)家 制造商全稱(chēng):未知廠(chǎng)家 功能描述:Two-Way Power Divider 10500 MHz |
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