DS3161/DS3162/DS3163/DS3164
18.7 CLAD Jitter Characteristics
PARAMETER
MIN
TYP
MAX
UNITS
Intrinsic Jitter (UIP-P)
0.025
UIP-P
Intrinsic Jitter (UIRMS)
0.0045
UIRMS
Peak Jitter Transfer
1.75
dB
18.8 JTAG Interface AC Characteristics
All AC timing characteristics are specified with a 50pF capacitive load on JTDO pin and 25pF capacitive load on all
other digital output pins, VIH = 2.4V and VIL = 0.8V. The voltage threshold for all timing measurements is VDD/2.
this interface.
Table 18-8. JTAG Interface Timing
(VDD = 3.3V ±5%, Tj = -40°C to +125°C.)
SIGNAL
NAME(S)
SYMBOL
DESCRIPTION
MIN TYP MAX
UNITS NOTES
JTCLK
f1
Clock Frequency (1/t1)
0
10
MHz
JTCLK
t2
Clock High or Low Period
20
ns
JTCLK
t3
Rise/Fall Times
5
ns
JTMS and
JTDI
t5
Hold Time from JTCLK Rising Edge
10
ns
JTMS and
JTDI
t6
Setup Time to JTCLK Rising Edge
10
ns
JTDO
t7
Delay from JTCLK Falling Edge
0
20
ns
JTDO
t8
Delay out of Hi-Z from JTCLK Falling
Edge
0
20
ns
JTDO
t9
Delay to Hi-Z from JTCLK Falling Edge
0
20
ns
Any Digital
Output
t7
Delay from JTCLK Falling Edge
0
20
ns
1
Any Digital
Output
t7
Delay from JTCLK Rising Edge
0
20
ns
2
Any Digital
Output
t8
Delay out of Hi-Z from JTCLK Falling
Edge
0
20
ns
1
Any Digital
Output
t9
Delay into Hi-Z from JTCLK Falling Edge
0
20
ns
1
Any Digital
Output
t8
Delay out of Hi-Z from JTCLK Rising
Edge
0
20
ns
2,3
Any Digital
Output
t9
Delay into Hi-Z from JTCLK Rising Edge
0
20
ns
2,3
Note 1:
Change during Update-DR state.
Note 2:
Change during Update-IR state to or from EXTEST mode.
Note 3:
Change during Update-IR state to or from HIZ mode.