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鍙冩暩(sh霉)璩囨枡
| 鍨嬭櫉锛� | DS3120N |
| 寤犲晢锛� | Maxim Integrated Products |
| 鏂囦欢闋佹暩(sh霉)锛� | 110/133闋� |
| 鏂囦欢澶�?銆�?/td> | 0K |
| 鎻忚堪锛� | IC FRAMER T1 28-CHANNEL IND |
| 妯欐簴鍖呰锛� | 1 |
| 鎺у埗鍣ㄩ鍨嬶細 | T1 瑾�(di脿o)骞€鍣� |
| 鎺ュ彛锛� | 骞惰/涓茶 |
| 闆绘簮闆诲锛� | 2.97 V ~ 3.63 V |
| 闆绘祦 - 闆绘簮锛� | 300mA |
| 宸ヤ綔婧害锛� | -40°C ~ 85°C |
| 瀹夎椤炲瀷锛� | 琛ㄩ潰璨艰 |
| 灏佽/澶栨锛� | 316-BGA |
| 鍖呰锛� | 绠′欢 |
绗�1闋�绗�2闋�绗�3闋�绗�4闋�绗�5闋�绗�6闋�绗�7闋�绗�8闋�绗�9闋�绗�10闋�绗�11闋�绗�12闋�绗�13闋�绗�14闋�绗�15闋�绗�16闋�绗�17闋�绗�18闋�绗�19闋�绗�20闋�绗�21闋�绗�22闋�绗�23闋�绗�24闋�绗�25闋�绗�26闋�绗�27闋�绗�28闋�绗�29闋�绗�30闋�绗�31闋�绗�32闋�绗�33闋�绗�34闋�绗�35闋�绗�36闋�绗�37闋�绗�38闋�绗�39闋�绗�40闋�绗�41闋�绗�42闋�绗�43闋�绗�44闋�绗�45闋�绗�46闋�绗�47闋�绗�48闋�绗�49闋�绗�50闋�绗�51闋�绗�52闋�绗�53闋�绗�54闋�绗�55闋�绗�56闋�绗�57闋�绗�58闋�绗�59闋�绗�60闋�绗�61闋�绗�62闋�绗�63闋�绗�64闋�绗�65闋�绗�66闋�绗�67闋�绗�68闋�绗�69闋�绗�70闋�绗�71闋�绗�72闋�绗�73闋�绗�74闋�绗�75闋�绗�76闋�绗�77闋�绗�78闋�绗�79闋�绗�80闋�绗�81闋�绗�82闋�绗�83闋�绗�84闋�绗�85闋�绗�86闋�绗�87闋�绗�88闋�绗�89闋�绗�90闋�绗�91闋�绗�92闋�绗�93闋�绗�94闋�绗�95闋�绗�96闋�绗�97闋�绗�98闋�绗�99闋�绗�100闋�绗�101闋�绗�102闋�绗�103闋�绗�104闋�绗�105闋�绗�106闋�绗�107闋�绗�108闋�绗�109闋�鐣跺墠绗�110闋�绗�111闋�绗�112闋�绗�113闋�绗�114闋�绗�115闋�绗�116闋�绗�117闋�绗�118闋�绗�119闋�绗�120闋�绗�121闋�绗�122闋�绗�123闋�绗�124闋�绗�125闋�绗�126闋�绗�127闋�绗�128闋�绗�129闋�绗�130闋�绗�131闋�绗�132闋�绗�133闋�
DS3112
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8
BERT
The BERT block can generate and detect the following patterns:
Pseudorandom patterns 2
7 - 1, 211 - 1, 215 - 1, and QRSS
A repetitive pattern from 1 to 32 bits in length
Alternating (16-bit) words that flip every 1 to 256 words
The BERT receiver has a 32-bit bit counter and a 24-bit error counter. It can generate interrupts on
detecting a bit error, a change in synchronization, or if an overflow occurs in the bit and error counters.
See Section 8.1 for details on status bits and interrupts from the BERT block. To activate the BERT
block, the host must configure the BERT mux via the BERT mux control register (Section 8.1). Data can
be routed to the receive side of the BERT from either the T3/E3 framer or from one of the 28 T1 or 16/21
E1 receive ports. Data from the transmit side of the BERT can be inserted either into the T3/E3 framer or
into one of the 28 T1 or 16/21 E1 transmit ports. See Figure 1-1 and Figure 1-2 for a visual description of
where data to and from the BERT can be placed.
8.1 BERT Register Description
Register Name:
BERTMC
Register Description:
BERT Mux Control Register
Register Address:
0x6Eh
Bit #
7
6
5
4
3
2
1
Name
RBPS3
RBPS2
RBPS1
0
鈥�
RBPS4
RBPS0
Default
0
鈥�
0
Bit #
15
14
13
12
11
10
9
8
Name
鈥�
TBPS4
TBPS3
TBPS2
TBPS1
TBPS0
Default
鈥�
0
Note: Bits that are underlined are read-only; all other bits are read-write.
Bits 0 to 4: Receive BERT Port Select Bits 0 to 4 (RBPS0 to RBPS4). These bits determine if data from any of
the 28 T1 or 16/21 E1 receive ports or the T3/E3 receive framer (with or without the overhead bits) will be routed
to the receive side of the BERT. If these bits are set to 11101, only the T3/E3 payload data will be routed to the
receive BERT. If these bits are set to 11110, all T3/E3 data (payload and the overhead bits) will be routed to the
receive BERT.
RBPS4:0
00000
No Data
01000
Port 8
00001
Port 1
01001
Port 9
00010
Port 2
01010
Port 10
00011
Port 3
01011
Port 11
00100
Port 4
01100
Port 12
00101
Port 5
01101
Port 13
00110
Port 6
01110
Port 14
00111
Port 7
01111
Port 15
10000
Port 16
11000
Port 24
10001
Port 17
11001
Port 25
10010
Port 18
11010
Port 26
10011
Port 19
11011
Port 27
10100
Port 20
11100
Port 28
10101
Port 21
11101
T3/E3 Framer (payload bits only)
10110
Port 22
11110
T3/E3 Framer (payload + overhead bits)
10111
Port 23
11111
Illegal State
鐩搁棞(gu膩n)PDF璩囨枡 |
PDF鎻忚堪 |
|---|---|
| DS31256+ | IC CTRLR HDLC 256-CHANNEL 256BGA |
| DS3141+ | IC FRAMER DS3/E3 SNGL 144CSBGA |
| DS31412N | IC 12CH DS3/3 FRAMER 349-BGA |
| DS3150TN | IC LIU T3/E3/STS-1 IND 48-TQFP |
| DS3154N+ | IC LIU DS3/E3/STS-1 QD 144CSBGA |
鐩搁棞(gu膩n)浠ｇ悊鍟�/鎶€琛�(sh霉)鍙冩暩(sh霉) |
鍙冩暩(sh霉)鎻忚堪 |
|---|---|
| DS3121 | 鍔熻兘鎻忚堪:IC TGATOR T1-T3 AGGREGATOR RoHS:鍚� 椤炲垾:闆嗘垚闆昏矾 (IC) >> 鎺ュ彛 - 鎺у埗鍣� 绯诲垪:- 妯欐簴鍖呰:4,900 绯诲垪:- 鎺у埗鍣ㄩ鍨�:USB 2.0 鎺у埗鍣� 鎺ュ彛:涓茶 闆绘簮闆诲:3 V ~ 3.6 V 闆绘祦 - 闆绘簮:135mA 宸ヤ綔婧害:0°C ~ 70°C 瀹夎椤炲瀷:琛ㄩ潰璨艰 灏佽/澶栨:36-VFQFN 瑁搁湶鐒婄洡 渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁�:36-QFN锛�6x6锛� 鍖呰:* 鍏跺畠鍚嶇ū:Q6396337A |
| DS3121N | 鍔熻兘鎻忚堪:IC TGATOR T1-T3 AGGREGATOR IND RoHS:鍚� 椤炲垾:闆嗘垚闆昏矾 (IC) >> 鎺ュ彛 - 鎺у埗鍣� 绯诲垪:- 妯欐簴鍖呰:4,900 绯诲垪:- 鎺у埗鍣ㄩ鍨�:USB 2.0 鎺у埗鍣� 鎺ュ彛:涓茶 闆绘簮闆诲:3 V ~ 3.6 V 闆绘祦 - 闆绘簮:135mA 宸ヤ綔婧害:0°C ~ 70°C 瀹夎椤炲瀷:琛ㄩ潰璨艰 灏佽/澶栨:36-VFQFN 瑁搁湶鐒婄洡 渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁�:36-QFN锛�6x6锛� 鍖呰:* 鍏跺畠鍚嶇ū:Q6396337A |
| DS31256 | 鍔熻兘鎻忚堪:杓稿叆/杓稿嚭鎺у埗鍣ㄦ帴鍙ｉ泦鎴愰浕璺� 256Ch High Thruput HDLC Cntlr RoHS:鍚� 鍒堕€犲晢:Silicon Labs 鐢�(ch菐n)鍝�: 杓稿叆/杓稿嚭绔暩(sh霉)閲�: 宸ヤ綔闆绘簮闆诲: 鏈€澶у伐浣滄韩搴�:+ 85 C 鏈€灏忓伐浣滄韩搴�:- 40 C 瀹夎棰ㄦ牸:SMD/SMT 灏佽 / 绠遍珨:QFN-64 灏佽:Tray |
| DS31256+ | 鍔熻兘鎻忚堪:杓稿叆/杓稿嚭鎺у埗鍣ㄦ帴鍙ｉ泦鎴愰浕璺� 256Ch High Thruput HDLC Cntlr RoHS:鍚� 鍒堕€犲晢:Silicon Labs 鐢�(ch菐n)鍝�: 杓稿叆/杓稿嚭绔暩(sh霉)閲�: 宸ヤ綔闆绘簮闆诲: 鏈€澶у伐浣滄韩搴�:+ 85 C 鏈€灏忓伐浣滄韩搴�:- 40 C 瀹夎棰ㄦ牸:SMD/SMT 灏佽 / 绠遍珨:QFN-64 灏佽:Tray |
| DS31256B | 鍔熻兘鎻忚堪:杓稿叆/杓稿嚭鎺у埗鍣ㄦ帴鍙ｉ泦鎴愰浕璺� 256Ch High Thruput HDLC Cntlr RoHS:鍚� 鍒堕€犲晢:Silicon Labs 鐢�(ch菐n)鍝�: 杓稿叆/杓稿嚭绔暩(sh霉)閲�: 宸ヤ綔闆绘簮闆诲: 鏈€澶у伐浣滄韩搴�:+ 85 C 鏈€灏忓伐浣滄韩搴�:- 40 C 瀹夎棰ㄦ牸:SMD/SMT 灏佽 / 绠遍珨:QFN-64 灏佽:Tray |
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