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參數(shù)資料
| 型號(hào)： | DS3120 |
| 廠商： | Maxim Integrated Products |
| 文件頁(yè)數(shù)： | 97/133頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC FRAMER T1 28-CHAN 0-70C DEG |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 控制器類型： | T1 調(diào)幀器 |
| 接口： | 并行/串行 |
| 電源電壓： | 2.97 V ~ 3.63 V |
| 電流 - 電源： | 300mA |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 316-BGA |
| 包裝： | 管件 |
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DS3112
66 of 133
Register Name:
T2E2SR2
Register Description:
T2/E2 Status Register 2
Register Address:
36h
Bit #
7
6
5
4
3
2
1
0
Name
IERAI
RAI7
RAI6
RAI5
RAI4
RAI3
RAI2
RAI1
Default
0
—
Bit #
15
14
13
12
11
10
9
8
Name
E2SOF4
E2SOF3
E2SOF2
E2SOF1
E2Sn4
E2Sn3
E2Sn2
E2Sn1
Default
—
Note: See Figure 6-2 for details on the signal flow for the status bits in the T2E2SR2 register. Bits that are underlined are read-only; all
other bits are read-write.
Bits 0 to 6: Remote Alarm Indication Signal Detected (RAIn when n = 1 to 7). This latched read-only alarm-
status bit will be set to a one each time the corresponding T2/E2/G.747 framer detects an incoming RAI alarm.
This bit will be cleared when read unless the RAI alarm still exists in that T2/E2/G.747 framer. A change in state of
the RAI in one or more of the T2/E2/G.747 framers can cause the T2E2SR2 status bit (in the MSR register) to be
set and a hardware interrupt to occur if the IERAI bit is set to a one and the T2E2SR2 bit in the Interrupt Mask for
MSR (IMSR) register is set to a one (Figure 6-2). The interrupt will be allowed to clear when this bit is read. The
RAI alarm criteria are described in Table 6-1, Table 6-2, and Table 6-3. In the E3 mode, RAI5 to RAI7 (bits 4 to 6)
are meaningless and should be ignored.
Bit 7: Interrupt Enable for Remote Alarm Indication Signal (IERAI). This bit should be set to one if the host
wishes to have RAI detection occurrences cause a hardware interrupt or the setting of the T2E2SR2 status bit in the
MSR register (Figure 6-2). The T2E2SR2 bit in the Interrupt Mask for the Master Status Register (IMSR) must
also be set to one for an interrupt to occur.
0 = interrupt masked
1 = interrupt unmasked
Bits 8 to 11: E2 Receive National Bit (E2Snn when n = 1 to 4). This read-only real-time status bit reports the
incoming E2 National Bit (Sn). It is loaded at the start of each E2 frame as the Sn bit is decoded. The host can use
the E2SOF status bit to determine when to read this bit. In the T3 and G.747 modes, this bit is meaningless and
should be ignored. This bit cannot cause an interrupt to occur.
Bits 12 to 15: E2 Receive Start Of Frame (E2SOFn where n = 1 to 4). This latched read-only event-status bit
will be set to a one on each E2 receive frame boundary. This bit will be cleared when read. The setting of this
status bit cannot cause an interrupt to occur.
Figure 6-2. T2E2SR2 Status Bit Flow
Alarm Latch
Change in State Detect
RAI1
(T2E2SR2
Bit 0)
Internal RAI
Signal from
T2/E2 Framer 1
Alarm Latch
Change in State Detect
Internal RAI
Signal from
T2/E2 Framer 2
Alarm Latch
Change in State Detect
Internal RAI
Signal from
T2 Framer 7
OR
Mask
IERAI
(T2E2SR2
Bit 7)
RAI2
(T2E2SR2
Bit 1)
RAI7
(T2E2SR2
Bit 6)
Mask
T2E2SR2
(IMSR Bit 6)
INT*
Hardware
Signal
T2E2SR2
Status Bit
(MSR Bit 6)
Event Latch
NOTE: ALL EVENT AND ALARM LATCHES ABOVE ARE CLEARED WHEN THE T2E2SR2 REGISTER IS READ.
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