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鍙冩暩(sh霉)璩囨枡
| 鍨嬭櫉锛� | DS3112D1+ |
| 寤犲晢锛� | Maxim Integrated Products |
| 鏂囦欢闋佹暩(sh霉)锛� | 2/133闋� |
| 鏂囦欢澶�?銆�?/td> | 0K |
| 鎻忚堪锛� | IC MUX T3/E3 3.3V 256-PBGA |
| 鐢�(ch菐n)鍝佸煿瑷�(x霉n)妯″锛� | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 妯�(bi膩o)婧�(zh菙n)鍖呰锛� | 40 |
| 鎺у埗鍣ㄩ鍨嬶細 | 瑾�(di脿o)骞€鍣�锛屽璺京(f霉)鐢ㄥ櫒 |
| 鎺ュ彛锛� | 骞惰/涓茶 |
| 闆绘簮闆诲锛� | 3.135 V ~ 3.465 V |
| 闆绘祦 - 闆绘簮锛� | 150mA |
| 宸ヤ綔婧害锛� | 0°C ~ 70°C |
| 瀹夎椤炲瀷锛� | 琛ㄩ潰璨艰 |
| 灏佽/澶栨锛� | 256-LBGA |
| 渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁濓細 | 256-PBGA锛�27x27锛� |
| 鍖呰锛� | 绠′欢 |
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DS3112
10 of 133
1.2.6 BERT
Can generate and detect the pseudorandom patterns of 2
7 - 1, 211 - 1, 215 - 1 and QRSS as well as
repetitive patterns from 1 to 32 bits in length
BERT is a global chip resource that can be used either in the T3/E3 data path or in any one of the T1
or E1 data paths
Large error counter (24 bits) allows testing to proceed for long periods without Host intervention
Errors can be inserted into the generated BERT patterns for diagnostic purposes
1.2.7 Diagnostics
T3/E3 and T1/E1 diagnostic loopbacks (transmit to receive)
T3/E3 and T1/E1 line loopbacks (receive to transmit)
T3/E3 payload loopback
T3/E3 errors counters for: BiPolar Violations (BPV), Code Violations (CV), Loss Of Frame (LOF),
framing bit errors (F, M or FAS), EXcessive Zeros (EXZ), T3 Parity bits, T3 C-Bit Parity, and Far
End Block Errors (FEBE)
Error counters can be either updated automatically on one second boundaries as timed by the DS3112
or via software control or via an external hardware pulse
Can insert the following T3/E3 errors: BiPolar Violations (BPV), EXcessive Zeros (EXZ), T3 Parity
bits, T3 C-Bit Parity, framing bit errors (F, M, or FAS)
Inserted errors can be either controlled via software or via an external hardware pulse
Generates T2/E2 Loss Of Frame (LOF)
1.2.8 Control Port
Nonmultiplexed or multiplexed 16-bit control port (with an optional 8-bit mode)
Intel and Motorola Bus compatible
1.2.9 Packaging and Power
3.3V low-power CMOS with 5V tolerant inputs and outputs
256-pin plastic BGA package (27mm x 27mm)
IEEE 1149.1 JTAG test port
鐩搁棞(gu膩n)PDF璩囨枡 |
PDF鎻忚堪 |
|---|---|
| 413959-6 | CONN PLUG BNC RG141 R/A CRIMP AU |
| VE-BTZ-IV-S | CONVERTER MOD DC/DC 2V 60W |
| VE-BTY-IV-S | CONVERTER MOD DC/DC 3.3V 99W |
| 227079-3 | CONN PLUG BNC RG59,62 CRIMP TIN |
| VE-2T1-IX-S | CONVERTER MOD DC/DC 12V 75W |
鐩搁棞(gu膩n)浠ｇ悊鍟�/鎶€琛�(sh霉)鍙冩暩(sh霉) |
鍙冩暩(sh霉)鎻忚堪 |
|---|---|
| DS3112D1+ | 鍔熻兘鎻忚堪:缍�(w菐ng)绲�(lu貌)鎺у埗鍣ㄨ垏铏曠悊鍣� IC TEMPE T3/E3 MUX FRMR & M13/E13/G.747 MUX RoHS:鍚� 鍒堕€犲晢:Micrel 鐢�(ch菐n)鍝�:Controller Area Network (CAN) 鏀剁櫦(f膩)鍣ㄦ暩(sh霉)閲�: 鏁�(sh霉)鎿�(j霉)閫熺巼: 闆绘簮闆绘祦锛堟渶澶у€硷級:595 mA 鏈€澶у伐浣滄韩搴�:+ 85 C 瀹夎棰�(f膿ng)鏍�:SMD/SMT 灏佽 / 绠遍珨:PBGA-400 灏佽:Tray |
| DS3112DK | 鍔熻兘鎻忚堪:缍�(w菐ng)绲�(lu貌)闁嬬櫦(f膩)宸ュ叿 DS3112 Dev Kit RoHS:鍚� 鍒堕€犲晢:Rabbit Semiconductor 鐢�(ch菐n)鍝�:Development Kits 椤炲瀷:Ethernet to Wi-Fi Bridges 宸ュ叿鐢ㄤ簬瑭曚及:RCM6600W 鏁�(sh霉)鎿�(j霉)閫熺巼:20 Mbps, 40 Mbps 鎺ュ彛椤炲瀷:802.11 b/g, Ethernet 宸ヤ綔闆绘簮闆诲:3.3 V |
| DS3112N | 鍔熻兘鎻忚堪:缍�(w菐ng)绲�(lu貌)鎺у埗鍣ㄨ垏铏曠悊鍣� IC TEMPE T3/E3 MUX FRMR & M13/E13/G.747 MUX RoHS:鍚� 鍒堕€犲晢:Micrel 鐢�(ch菐n)鍝�:Controller Area Network (CAN) 鏀剁櫦(f膩)鍣ㄦ暩(sh霉)閲�: 鏁�(sh霉)鎿�(j霉)閫熺巼: 闆绘簮闆绘祦锛堟渶澶у€硷級:595 mA 鏈€澶у伐浣滄韩搴�:+ 85 C 瀹夎棰�(f膿ng)鏍�:SMD/SMT 灏佽 / 绠遍珨:PBGA-400 灏佽:Tray |
| DS3112N+ | 鍔熻兘鎻忚堪:缍�(w菐ng)绲�(lu貌)鎺у埗鍣ㄨ垏铏曠悊鍣� IC TEMPE T3/E3 MUX FRMR & M13/E13/G.747 MUX RoHS:鍚� 鍒堕€犲晢:Micrel 鐢�(ch菐n)鍝�:Controller Area Network (CAN) 鏀剁櫦(f膩)鍣ㄦ暩(sh霉)閲�: 鏁�(sh霉)鎿�(j霉)閫熺巼: 闆绘簮闆绘祦锛堟渶澶у€硷級:595 mA 鏈€澶у伐浣滄韩搴�:+ 85 C 瀹夎棰�(f膿ng)鏍�:SMD/SMT 灏佽 / 绠遍珨:PBGA-400 灏佽:Tray |
| DS3112N+W | 鍔熻兘鎻忚堪:缍�(w菐ng)绲�(lu貌)鎺у埗鍣ㄨ垏铏曠悊鍣� IC TEMPE T3/E3 MUX FRMR & M13/E13/G.747 MUX RoHS:鍚� 鍒堕€犲晢:Micrel 鐢�(ch菐n)鍝�:Controller Area Network (CAN) 鏀剁櫦(f膩)鍣ㄦ暩(sh霉)閲�: 鏁�(sh霉)鎿�(j霉)閫熺巼: 闆绘簮闆绘祦锛堟渶澶у€硷級:595 mA 鏈€澶у伐浣滄韩搴�:+ 85 C 瀹夎棰�(f膿ng)鏍�:SMD/SMT 灏佽 / 绠遍珨:PBGA-400 灏佽:Tray |
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