參數(shù)資料
型號(hào)： DS2760AX
廠商： MAXIM INTEGRATED PRODUCTS INC
元件分類(lèi)： 電源管理
英文描述： 1-CHANNEL POWER SUPPLY SUPPORT CKT, PBGA14
封裝： FLIPCHIP-14
文件頁(yè)數(shù)： 4/25頁(yè)
文件大?。?/td> 289K
代理商： DS2760AX
DS2760
12
COC – Charge Overcurrent Flag. When set to 1, this bit indicates the battery pack has experienced a
charge-direction overcurrent condition. This bit must be reset by the host system.
DOC – Discharge Overcurrent Flag. When set to 1, this bit indicates the battery pack has experienced a
discharge-direction overcurrent condition. This bit must be reset by the host system.
CC – CC Pin Mirror. This read-only bit mirrors the state of the CC output pin.
DC – DC Pin Mirror. This read-only bit mirrors the state of the DC output pin.
CE – Charge Enable. Writing a 0 to this bit disables charging ( CC output high, external charge FET off)
regardless of cell or pack conditions. Writing a 1 to this bit enables charging, subject to override by the
presence of any protection conditions. The DS2760 automatically sets this bit to 1 when it transitions
from Sleep Mode to Active Mode.
DE – Discharge Enable. Writing a 0 to this bit disables discharging ( DC output high, external discharge
FET off) regardless of cell or pack conditions. Writing a 1 to this bit enables discharging, subject to
override by the presence of any protection conditions. The DS2760 automatically sets this bit to 1 when
it transitions from Sleep Mode to Active Mode.
STATUS REGISTER
The default values for the Status Register bits are stored in lockable EEPROM in the corresponding bits
of address 31h. A Recall Data command for EEPROM block 1 recalls the default values into the Status
Register bits. The format of the Status Register is shown in Figure 10. The function of each bit is
described in detail in the following paragraphs.
STATUS REGISTER FORMAT Figure 10
Address 01
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
X
PMOD RNAOP SWEN
X
PMOD – Sleep Mode Enable. A value of 1 in this bit enables the DS2760 to enter Sleep Mode when the
DQ line goes low for greater than 2 seconds and leave Sleep Mode when the DQ line goes high. A value
of 0 disables DQ-related transitions into and out of Sleep Mode. This bit is read-only. The desired
default value should be set in bit 5 of address 31h. The factory default is 0.
RNAOP – Read Net Address Opcode. A value of 0 in this bit sets the opcode for the Read Net Address
command to 33h, while a 1 sets the opcode to 39h. This bit is read-only. The desired default value should
be set in bit 4 of address 31h. The factory default is 0.
SWEN - SWAP Command Enable. A value of 1 in this bit location enables the recognition of a SWAP
command. If set to 0, SWAP commands are ignored. The desired default value should be set in bit 3 of
address 31h. This bit is read-only. The factory default is 0.
X – Reserved bits.
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
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