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參數(shù)資料
| 型號(hào)： | DS2720CU |
| 英文描述： | Efficient, Addressable Single-Cell Rechargeable Lithium Protection IC |
| 中文描述： | 高效，尋址單節(jié)可充電鋰電池保護(hù)IC |
| 文件頁數(shù)： | 17/21頁 |
| 文件大?。?/td> | 252K |
| 代理商： | DS2720CU |
DS2720
17 of 21
I/O SIGNALING
The 1-Wire bus requires strict signaling protocols to insure data integrity. The four protocols used by the
DS2720 are the initialization sequence (reset pulse followed by presence pulse), write 0, write 1, and read
data. All of these types of signaling except the presence pulse are initiated by the bus master.
The initialization sequence required to begin any communication with the DS2720 is shown in Figure 12.
A presence pulse following a reset pulse indicates the DS2720 is ready to accept a net address command.
The bus master transmits (Tx) a reset pulse for t
RSTL
. The bus master then releases the line and goes into
receive mode (Rx). The 1-Wire bus line is then pulled high by the pullup resistor. After detecting the
rising edge on the DQ pin, the DS2720 waits for t
PDH
and then transmits the presence pulse for t
PDL
.
Figure 12.
1-WIRE INITIALIZATION SEQUENCE
WRITE-TIME SLOTS
A write-time slot is initiated when the bus master pulls the 1-Wire bus from a logic-high (inactive) level
to a logic-low level. There are two types of write-time slots: write 1 and write 0. All write-time slots must
be t
SLOT
(60 s to 120 s) in duration with a 1 s minimum recovery time, t
REC
, between cycles. The
DS2720 samples the 1-Wire bus line between 15 s and 60 s after the line falls. If the line is high when
sampled, a write 1 occurs. If the line is low when sampled, a write 0 occurs (see Figure 13). For the bus
master to generate a write 1 time slot, the bus line must be pulled low and then released, allowing the line
to be pulled high within 15 s after the start of the write time slot. For the host to generate a write 0 time
slot, the bus line must be pulled low and held low for the duration of the write-time slot.
READ-TIME SLOTS
A read-time slot is initiated when the bus master pulls the 1-Wire bus line from a logic-high level to a
logic-low level. The bus master must keep the bus line low for at least 1 s and then release it to allow the
DS2720 to present valid data. The bus master can then sample the data t
RDV
(15 s) from the start of the
read-time slot. By the end of the read-time slot, the DS2720 releases the bus line and allows it to be
pulled high by the external pullup resistor. All read-time slots must be t
SLOT
(60 s to 120 s) in duration
with a 1 s minimum recovery time, t
REC
, between cycles. See Figure 13 for more information.
t
RSTL
t
PDL
t
RSTH
t
PDH
V
DQ
V
SS
LINE TYPE LEGEND:
BUS MASTER ACTIVE LOW
DS2720 ACTIVE LOW
RESISTOR PULLUP
BOTH BUS MASTER AND
DS2720 ACTIVE LOW
DQ
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| DS2722-F-03 | 900MHz Low-IF 1.5Mbps FSK Transceiver Final Datasheet |
| DS2722-F-04 | 900MHz Low-IF 1.5Mbps FSK Transceiver Final Datasheet |
| DS2722-F-05 | 900MHz Low-IF 1.5Mbps FSK Transceiver Final Datasheet |
| DS2740 | High-Precision Coulomb Counter |
| DS2740B | High-Precision Coulomb Counter |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| DS2720CU+ | 制造商:Maxim Integrated Products 功能描述:PROT LI-ION 4.3V 8USOP - Rail/Tube |
| DS2720CU+T&R | 制造商:Maxim Integrated Products 功能描述:PROT LI-ION 4.3V 8USOP - Tape and Reel 制造商:Maxim Integrated Products 功能描述:IC LITH BATTERY PROTECT 8-USOP |
| DS2720CU+T&R | 功能描述:IC LITH BATTERY PROTECT 8-USOP RoHS:是 類別:集成電路 (IC) >> PMIC - 電池管理 系列:- 標(biāo)準(zhǔn)包裝:1 系列:- 功能:充電管理 電池化學(xué):鋰離子（Li-Ion）、鋰聚合物（Li-Pol） 電源電壓:3.75 V ~ 6 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:SC-74A，SOT-753 供應(yīng)商設(shè)備封裝:SOT-23-5 包裝:剪切帶 (CT) 產(chǎn)品目錄頁面:669 (CN2011-ZH PDF) 其它名稱:MCP73831T-2ACI/OTCT |
| DS2720K | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Li+ Battery Protector Evaluation Kit |
| DS2722-F-03 | 制造商:MICRO-LINEAR 制造商全稱:MICRO-LINEAR 功能描述:900MHz Low-IF 1.5Mbps FSK Transceiver Final Datasheet |
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