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參數(shù)資料
| 型號(hào)： | DS26528G+ |
| 廠商： | Maxim Integrated Products |
| 文件頁(yè)數(shù)： | 201/276頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC TXRX T1/E1/J1 OCT 256-CSBGA |
| 產(chǎn)品培訓(xùn)模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標(biāo)準(zhǔn)包裝： | 90 |
| 類型： | 收發(fā)器 |
| 驅(qū)動(dòng)器/接收器數(shù)： | 4/4 |
| 規(guī)程： | IEEE 1149.1 |
| 電源電壓： | 3.135 V ~ 3.465 V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 256-LBGA，CSBGA |
| 供應(yīng)商設(shè)備封裝： | 256-CSBGA（17x17） |
| 包裝： | 托盤 |
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DS26528 Octal T1/E1/J1 Transceiver
30 of 276
8.4
Initialization and Configuration
8.4.1
Example Device Initialization Sequence
STEP 1: Reset the device by pulling the
RESETB pin low, applying power to the device, or by using the software
reset bits outlined in Section 8.3. Clear all reset bits. Allow time for the reset recovery.
STEP 2: Check the device ID in the Device Identification register (IDR).
STEP 3: Write the GTCCR register to correctly configure the system clocks. If supplying a 1.544MHz MCLK, follow
this write with at least a 300ns delay to allow the clock system to properly adjust.
STEP 4: Write the entire remainder of the register space for each port with 00h, including reserved register
locations.
STEP 5: Choose T1/J1 or E1 operation for the framers by configuring the T1/E1 bit in the TMMR and RMMR
registers for each framer. Set the FRM_EN bit to 1 in the TMMR and RMMR registers. If using software transmit
signaling in E1 mode, program the E1TAF and E1TNAF registers as required. Configure the framer Transmit
STEP 6: Choose T1/J1 or E1 operation for the LIUs by configuring the T1J1E1S bit in the LTRCR register.
Configure the line build-out for each LIU. Configure other LIU features as appropriate. Set the TE bit to turn on the
TTIP and TRING outputs.
STEP 7: Configure the elastic stores, HDLC controller, and BERT as needed.
8.5
Global Resources
All eight framers share a common microprocessor port. All ports share a common MCLK, and there is a common
software-configurable BPCLK output. A set of global registers are located at 0F0h–0FFh and include global resets,
global interrupt status, interrupt masking, clock configuration, and the device ID registers. See the global register
definitions in Table 9-2. A common JTAG controller is used.
8.6
Per-Port Resources
Each port has an associated framer, LIU, BERT, jitter attenuator, and transmit/receive HDLC controller. Each of the
per-port functions has its own register space.
8.7
Device Interrupts
Figure 8-2 diagrams the flow of interrupt conditions from their source status bits through the multiple levels of
information registers and mask bits to the interrupt pin. When an interrupt occurs, the host can read the global
interrupt information registers GFISR, GLISR, and GBISR to identify which of the eight transceivers is causing the
interrupt(s). The host can then read the specific transceiver’s interrupt information registers (TIIR, RIIR) and the
latched status registers (LLSR, BLSR) to further identify the source of the interrupt(s). If TIIR or RIIR is the source,
the host will then read the transmit-latched status or the receive-latched status registers for the source of the
interrupt. All interrupt information register bits are real-time bits that clear once the appropriate interrupt has been
serviced and cleared, as long as no additional, unmasked interrupt condition is present in the associated status
register. The host must clear all latched status bits by writing a 1 to the bit location of the interrupt condition that
has been serviced. Latched status bits that have been masked by the interrupt mask registers are masked from the
interrupt information registers. The interrupt mask register bits prevent individual latched status conditions from
generating an interrupt, but they do not prevent the latched status bits from being set. Therefore, when servicing
interrupts, the user should XOR the latched status with the associated interrupt mask in order to exclude bits for
which the user wished to prevent interrupt service. This architecture allows the application host to periodically poll
the latched status bits for noninterrupt conditions, while using only one set of registers.
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相關(guān)代理商/技術(shù)參數(shù) |
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| DS26528G+ | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC 8-Port E1/T1/J1 Transceiver RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| DS26528GA2 | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| DS26528GA3 | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| DS26528GA4 | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| DS26528GA5 | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC 8-Port E1/T1/J1 Transceiver RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
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