DS26521 Single T1/E1/J1 Transceiver
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Table 8-29. Recommended Supply Decoupling
SUPPLY PINS
DECOUPLING
CAPACITANCE
NOTES
DVDD/DVSS
0.1
μF + 0.1μF + 1μF + 10μF
—
DVDDIO/DVSSIO
0.1
μF + 0.1μF + 1μF + 10μF
—
ATVDD/ATVSS
(0.1
μF + 1μF + 10μF) x 4
Place set of three capacitors on each side of the
device.
ARVDD/ARVSS
(0.1
μF + 1μF + 10μF) x 4
Place set of three capacitors on each side of the
device.
ACVDD/ACVSS
0.1
μF + 1μF + 10μF
—
8.11.1 LIU Operation
The analog AMI/HDB3 waveforms off of the E1 lines or the AMI/B8ZS waveform off of the T1 lines are transformer
coupled into the RTIP and RRING pins of the DS26521. The user has the option to use internal termination,
software selectable for 75
Ω/100Ω/110Ω/120Ω applications, or external termination. The LIU recovers clock and
data from the analog signal and passes it through the jitter attenuation mux. The DS26521 contains an active filter
that reconstructs the analog received signal for the nonlinear losses that occur in transmission. The receive
circuitry also is configurable for various monitor applications. The device has a usable receive sensitivity of 0dB to
-43dB for E1 and 0dB to -36dB for T1, which allows the device to operate on 0.63mm (22AWG) cables up to 2.5km
(E1) and 6k feet (T1) in length. Data input to the transmit side of the LIU is sent via the jitter attenuation mux to the
waveshaping circuitry and line driver. The DS26521 drives the E1 or T1 line from the TTIP and TRING pins via a
coupling transformer. The line driver can handle both CEPT 30/ISDN-PRI lines for E1 and long-haul (CSU) or
short-haul (DSX-1) lines for T1. The registers that control the LIU operation are shown in
Table 8-30.Table 8-30. Registers Related to Control of DS26521 LIU
REGISTER
FRAMER
ADDRESSES
FUNCTION
Global Transceiver Control Register 2
0F2h
Global transceiver control.
Global Transceiver Clock Control Register
0F3h
MPS selections, backplane clock
selections
Global LIU Software Reset Register
0F5h
Software reset control for the LIU.
Global LIU Interrupt Status Register
0FBh
Interrupt status bit for the LIU.
Global LIU Interrupt Mask Register
0FEh
Interrupt mask register for the LIU.
LIU Transmit Receive Control Register
1000h
T1/J1/E1 selection, output tri-state, loss
criteria.
LIU Transmit Impedance and Pulse Shape
1001h
Transmit pulse shape and impedance
selection.
LIU Maintenance Control Register (
LMCR)
1002h
Transmit maintenance and jitter
attenuation control register.
LIU Real Status Register (
LRSR)
1003h
LIU real-time status register.
LIU Status Interrupt Mask Register
1004h
LIU mask registers based on latched
status bits.
LIU Latched Status Register
(LLSR)1005h
LIU latched status bits related to loss, open
circuit, etc.
LIU Receive Signal Level Register
(LRSL)1006h
LIU receive signal level indicator.
LIU Receive Impedance and Sensitivity
1007h
LIU impedance match and sensitivity
monitor.