DS26518 8-Port T1/E1/J1 Transceiver
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NAME
PIN
TYPE
FUNCTION
TSYNC8/
TSSYNCIO8
A13
be generated. This pulse in combination with BPCLK1 can be used as an IBO
master. TSSYNCIOn can be used as a source to RSYNCn and TSSYNCIOn of
another DS26518 or RSYNC and TSSYNC of other Maxim parts. Note:
TSSYNCIO[8:1] are not used when GTCR1.528MD is set. When GTCR1.528MD is set, the TSSYNCIO pin (N13) is used.
TSSYNCIO
N13
Input/
Output
Note: In default operation, this pin is not used. When GTCR1.528MD is set, this pin is active. If pin is not used, tie low through a resistor.
Transmit System Synchronization In. This pin is selected when the transmit-
side elastic store is enabled. A pulse at this pin establishes either frame or
multiframe boundaries for the transmit side. Note that if the elastic store is
enabled, frame or multiframe boundary will be established for all transmitters.
Should be tied low in applications that do not use the transmit-side elastic store.
The operation of this signal is synchronous with TSYSCLKn.
Transmit System Synchronization Out. If configured as an output and the
transmit-side elastic store is enabled, an 8kHz pulse synchronous to BPCLK1 will
be generated. This pulse in combination with BPCLK1 can be used as an IBO
master. TSSYNCIO can be used as a source to RSYNCn and TSSYNCIO of
another DS26518 or RSYNC and TSSYNC of other Maxim parts.
TSIG1
D5
TSIG2
A6
TSIG3
T4
TSIG4
R6
TSIG5
T10
TSIG6
R12
TSIG7
A11
TSIG8
C13
Input
Transmit Signaling 1 to 8. When enabled, this input samples signaling bits for
insertion into outgoing PCM data stream. Sampled on the falling edge of TCLKn
when the transmit-side elastic store is disabled. Sampled on the falling edge of
TSYSCLKn when the transmit-side elastic store is enabled. In IBO mode, the
TSIGn streams can run up to 16.384MHz. See
Table 9-9.
TCHBLK1/
TCHCLK1
A5
TCHBLK2/
TCHCLK2
C7
TCHBLK3/
TCHCLK3
L7
TCHBLK4/
TCHCLK4
P7
TCHBLK5/
TCHCLK5
P9
TCHBLK6/
TCHCLK6
P11
TCHBLK7/
TCHCLK7
D10
TCHBLK8/
TCHCLK8
E11
Output
Transmit Channel Block/Transmit Channel Block Clock. A dual function pin.
TCHBLK[1:8]. TCHBLKn is a user-programmable output that can be forced high
or low during any of the channels. It is synchronous with TCLKn when the
transmit-side elastic store is disabled. It is synchronous with TSYSCLKn when
the transmit-side elastic store is enabled. It is useful for blocking clocks to a serial
UART or LAPD controller in applications where not all channels are used such as
Fractional T1, Fractional E1, 384kbps (H0), 768kbps, or ISDN-PRI. Also useful
for locating individual channels in drop-and-insert applications, for external per-
channel loopback, and for per-channel conditioning.
TCHCLK[1:8]. TCHCLKn is a 192kHz (T1) or 256kHz (E1) clock that pulses high
during the LSB of each channel. It can also be programmed to output a gated
transmit bit clock controlled by TCHBLKn. It is synchronous with TCLKn when the
transmit-side elastic store is disabled. It is synchronous with TSYSCLKn when
the transmit-side elastic store is enabled. Useful for parallel-to-serial conversion
of channel data.