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參數(shù)資料
| 型號(hào)： | DS26514GN+ |
| 廠商： | Maxim Integrated Products |
| 文件頁數(shù)： | 279/305頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC TXRX T1/E1/J1 4PORT 256-CSBGA |
| 產(chǎn)品培訓(xùn)模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標(biāo)準(zhǔn)包裝： | 90 |
| 類型： | 收發(fā)器 |
| 驅(qū)動(dòng)器/接收器數(shù)： | 4/4 |
| 規(guī)程： | 以太網(wǎng) |
| 電源電壓： | 3.14 V ~ 3.47 V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 256-BGA，CSBGA |
| 供應(yīng)商設(shè)備封裝： | 256-CSBGA（17x17） |
| 包裝： | 托盤 |
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DS26514 4-Port T1/E1/J1 Transceiver
19-5856; Rev 4; 5/11
75 of 305
REGISTER
FRAMER 1
ADDRESSES
FUNCTION
Transmit Interrupt Mask Register 2
1A1h
Interrupt Mask for the Latched Status
Transmit HDLC-64 FIFO Buffer
Available
1B3h
Indicates the number of bytes that can be
written into the Transmit FIFO
Transmit HDLC-64 FIFO (THF)
1B4h
Transmit HDLC FIFO
Note: The addresses shown are for Framer 1. Addresses for Framers 2 to 4 can be calculated using the following: Framer n = (Framer 1
address + (n - 1) x 200hex); where n = 2 to 4 for Framers 2 to 4.
9.10.1.1
HDLC-64 FIFO Control
Control of the transmit and receive FIFOs is accomplished via the Receive HDLC-64 FIFO Control (RHFC) and
Transmit HDLC-64 FIFO Control (THFC) registers. The FIFO Control registers set the watermarks for the FIFO.
When the receive FIFO fills above the high watermark, the RHWM bit (RRTS5.1) will be set. RHWM and TLWM
are real-time bits and will remain set as long as the FIFO’s write pointer is above the watermark. When the transmit
FIFO empties below the low watermark, the TLWM bit in the TRTS2 register will be set. TLWM is a real-time bit
and will remain set as long as the transmit FIFO’s write pointer is below the watermark. If enabled, this condition
can also cause an interrupt via the INTB pin.
If the receive HDLC FIFO does overrun, the current packet being processed is dropped and the receive FIFO will
9.10.1.2
Receive Packet Bytes Available
The lower 7 bits of the Receive HDLC Packet Bytes Available Register (RHPBA) indicates the number of bytes (0
to 64) that can be read from the receive FIFO. The value indicated by this register informs the host as to how many
bytes can be read from the receive FIFO without going past the end of a message. This value will refer to one of
four possibilities, the first part of a packet, the continuation of a packet, the last part of a packet, or a complete
packet. After reading the number of bytes indicated by this register the host then checks the HDLC status registers
for detailed message status.
If the value in the RHPBA register refers to the beginning portion of a message or continuation of a message, then
the MSB of the RHPBA register will return a value of 1. This indicates that the host can safely read the number of
bytes returned by the lower 7 bits of the RHPBA register, but there is no need to check the information register
since the packet has not yet terminated (successfully or otherwise).
9.10.1.3
HDLC-64 Status and Information
RRTS5, RLS5, and TLS2 provide status information for the HDLC controller. When a particular event has occurred
(or is occurring), the appropriate bit in one of these registers will be set to a one. Some of the bits in these registers
are latched and some are real-time bits that are not latched. This section contains register descriptions that list
which bits are latched and which are real-time. With the latched bits, when an event occurs and a bit is set to a
one, it will remain set until the user reads and clears that bit. The bit will be cleared when a 1 is written to the bit
and it will not be set again until the event has occurred again. The real-time bits report the current instantaneous
conditions that are occurring and the history of these bits is not latched.
Like the other latched status registers, the user will follow a read of the status bit with a write. The byte written to
the register will inform the device which of the latched bits the user wishes to clear (the real-time bits are not
affected by writing to the status register). The user will write a byte to one of these registers, with a one in the bit
positions he or she wishes to clear and a zero in the bit positions he or she does not wish to clear.
INTB output
signal. Each of the events in this register can be either masked or unmasked from the interrupt pin via the HDLC
INTB signal low when the event occurs. The INTB
pin will be allowed to return high (if no other interrupts are present) when the user reads the event bit that caused
the interrupt to occur.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| DS26514GN+ | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC 4-Port E1/T1/J1 Transceiver RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| DS26518 | 制造商:MAXIM 制造商全稱:Maxim Integrated Products 功能描述:8-Port T1/E1/J1 Transceiver |
| DS26518DK | 功能描述:網(wǎng)絡(luò)開發(fā)工具 DS26518 Dev Kit RoHS:否 制造商:Rabbit Semiconductor 產(chǎn)品:Development Kits 類型:Ethernet to Wi-Fi Bridges 工具用于評(píng)估:RCM6600W 數(shù)據(jù)速率:20 Mbps, 40 Mbps 接口類型:802.11 b/g, Ethernet 工作電源電壓:3.3 V |
| DS26518G+ | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| DS26518GA2+ | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
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