
DS26514 4-Port T1/E1/J1 Transceiver
19-5856; Rev 4; 5/11
24 of 305
NAME
PIN
TYPE
FUNCTION
RCHBLK1/
RCHCLK1
E4
Output
Receive Channel Block/Receive Channel Block Clock. This pin can be
configured to output either RCHBLK or RCHCLK.
RCHBLK[1:4]. RCHBLKn is a user-programmable output that can be forced high
or low during any of the 24 T1 or 32 E1 channels. It is synchronous with RCLKn
when the receive-side elastic store is disabled. It is synchronous with RSYSCLKn
when the receive-side elastic store is enabled. This pin is useful for blocking
clocks to a serial UART or LAPD controller in applications where not all channels
are used such as fractional service, 384kbps service, 768kbps, or ISDN-PRI. Also
useful for locating individual channels in drop-and-insert applications, for external
per-channel loopback, and for per-channel conditioning.
RCHCLK[1:4]. RCHCLKn is a 192kHz (T1) or 256kHz (E1) clock that pulses high
during the LSB of each channel. It is synchronous with RCLKn when the receive-
side elastic store is disabled. It is synchronous with RSYSCLKn when the
receive-side elastic store is enabled. It is useful for parallel-to-serial conversion of
channel data.
RCHBLK2/
RCHCLK2
B5
RCHBLK3/
RCHCLK3
L6
RCHBLK4/
RCHCLK4
T5
BPCLK1
E8
Output
Backplane Clock 1. Programmable clock output that can be set to 2.048MHz,
4.096MHz, 8.192MHz, or 16.384MHz. The reference for this clock can be
RCLK[8:1], a 1.544MHz or 2.048MHz clock frequency derived from MCLK, or an
external reference clock (REFCLKIO). This allows system clocks to be referenced
from external sources, the T1J1E1 recovered clocks, or the MCLK oscillator.
CLKO/
RLF/LTC1
D3
Output
Clock Out. Clock output pin that can be programmed to output numerous
frequencies referenced to MCLK. Frequencies available: 1.544MHz, 2.048MHz,
4.096MHz, 8.192MHz, 12.288MHz, 16.384MHz, 256kHz, and 64kHz.
GTCCR3.CLKOSEL[2:0] selects the frequency.
Receive Loss of Frame/Loss of Transmit Clock. This pin can also be
programmed to either toggle high when the synchronizer is searching for the
frame and multiframe, or to toggle high if the TCLKn pin has not been toggled for
approximately three clock periods.
RLF/LTC1 is available on the DS26514 when
GTCR1.528MD = 1.
MICROPROCESSOR INTERFACE
A12
C8
Input
Address [12:0]. This bus selects a specific register in the DS26514 during
read/write access. A12 is the MSB and A0 is the LSB.
A11
A8
A10
B8
A9
F8
A8
B9
A7
A9
A6
C9
A5
D9
A4
E9
A3
F9
A2
B10
A1
A10
A0
C10
D[7]/SPI_CPOL
T9
Input/
Output
Data [7]/SPI Interface Clock Polarity
D[7]: Bit 7 of the 16-bit or 8-bit data bus used to input data during register writes
and data outputs during register reads. Not driven when
CSB = 1.
SPI_CPOL: This signal selects the clock polarity when SPI_SEL = 1. See Section
9.1.2 for detailed timing and functionality information. Default setting is low.
D[6]/SPI_CPHA
N9
Input/
Output
Data [6]/SPI Interface Clock Phase
D[6]: Bit 6 of the 16-bit or 8-bit data bus used to input data during register writes
and data outputs during register reads. Not driven when
CSB = 1.
SPI_CPHA: This signal selects the clock phase when SPI_SEL = 1. See Section
9.1.2 for detailed timing and functionality information. Default setting is low.