參數(shù)資料
型號: DS2436Z
廠商: DALLAS SEMICONDUCTOR
元件分類: Memory IC:Other
英文描述: SPECIALTY MEMORY CIRCUIT, PDSO8
封裝: 0.150 INCH, SOIC-8
文件頁數(shù): 17/29頁
文件大?。?/td> 505K
代理商: DS2436Z
DS2436
24 of 29
Read Time Slots
The host generates read time slots when data is to be read from the DS2436. A read time slot is initiated
when the host pulls the data line from a logic high level to logic low level. The data line must remain at a
low logic level for a minimum of 1
s; output data from the DS2436 is then valid for the next 14 s
maximum. The host therefore must stop driving the I/O pin low in order to read its state 15
s from the
start of the read slot (see Figure 9). By the end of the read time slot, the I/O pin will pull back high via the
external pullup resistor. All read time slots must be a minimum of 60
s in duration with a minimum
recovery time of 1
s between individual read slots.
Figure 10 shows that the sum of TINIT, TRC, and TSAMPLE must be less than 15
s. Figure 11 shows that
system timing margin is maximized by keeping TINIT and TRC as small as possible and by locating the
master sample time towards the end of the 15
s period.
INITIALIZATION PROCEDURE “RESET AND PRESENCE PULSES” Figure 8
LINE TYPE LEGEND:
Bus master active low
DS2436 active low
Both bus master and
DS2436 active low
Resistor pullup
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
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