參數(shù)資料
型號: DS2423X
廠商: DALLAS SEMICONDUCTOR
元件分類: Memory IC:Other
英文描述: SPECIALTY MEMORY CIRCUIT, UUC
封裝: CHIP SCALE PKG
文件頁數(shù): 18/25頁
文件大?。?/td> 579K
代理商: DS2423X
DS2422/DS2423
25 of 25
NOTES:
1. All voltages are referenced to ground.
2. VPUP = external pullup voltage.
3. Input load is to ground.
4. An additional reset or communication sequence cannot begin until the reset high time has expired.
5. Read data setup time refers to the time the host must pull the 1-Wire bus low to read a bit. Data is
guaranteed to be valid within 1 s of this falling edge.
6. Capacitance on the data pin could be 800 pF when power is first applied. If a 5 kO resistor is used to
pull up the data line to VPUP, 5 s after power has been applied the parasite capacitance will not affect
normal communications.
7. The reset low time (tRSTL) should be restricted to a maximum of 960 s, to allow interrupt signaling,
otherwise, it could mask or conceal interrupt pulses.
8. VIH is a function of the external pullup resistor and VPUP.
9. Under certain low voltage conditions VILMAX may have to be reduced to as much as 0.5V to always
guarantee a presence pulse.
10. The counter inputs are designed for interfacing to mechanical switches and piezo sensors. If
interfacing to digital circuits, one should use an open drain driver.
11. A lower impedance pullup, e. g., for reed switches, can be achieved by connecting an external resistor
from the counter input to VBAT.
12. Read and write scratchpad (all 32 bytes) at VBAT of 3.0 V.
13. Each low-going edge on a counter input resets the channel’s debounce timer. The debounce time
starts as the input voltage rises beyond the trip point. In order for the next pulse to be counted the
debounce time must have expired.
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