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參數(shù)資料
| 型號(hào)： | DS2423X |
| 元件分類： | 通用總線功能 |
| 英文描述： | 4kbit 1-Wire RAM with Counter |
| 中文描述： | 4kbit的1 - Wire與反內(nèi)存 |
| 文件頁數(shù)： | 19/25頁 |
| 文件大?。?/td> | 331K |
| 代理商： | DS2423X |
DS2423
19 of 25
1-WIRE SIGNALING
The DS2423 requires strict protocols to ensure data integrity. The protocol consists of four types of
signaling on one line: Reset Sequence with Reset Pulse and Presence Pulse, Write 0, Write 1 and Read
Data. The bus master initiates all these signals except Presence Pulse. The DS2423 can communicate at
two different speeds, regular speed and Overdrive speed. If not explicitly set into the Overdrive mode, the
DS2423 will communicate at regular speed. While in Overdrive mode the fast timing applies to all
waveforms.
The initialization sequence required to begin any communication with the DS2423 is shown in Figure 10.
A Reset Pulse followed by a Presence Pulse indicates the DS2423 is ready to send or receive data given
the correct ROM command and memory function command. The bus master transmits (TX) a Reset
Pulse (t
RSTL
, minimum 480 μs at regular speed, 48 μs at Overdrive speed). The bus master then releases
the line and goes into receive mode (RX). The 1-Wire bus is pulled to a high state via the pullup resistor.
After detecting the rising edge on the data pin, the DS2423 waits (t
PDH
, 15-60μs at regular speed, 2-6μs at
Overdrive speed) and then transmits the Presence Pulse (t
PDL
, 60-240μs at regular speed, 8-24μs at
Overdrive speed).
A Reset Pulse of 480μs or longer will exit the Overdrive mode returning the device to regular speed. If
the DS2423 is in Overdrive mode and the Reset Pulse is no longer than 80μs the device will remain in
Overdrive mode.
Read/Write Time Slots
The definitions of write and read time slots are illustrated in Figure 11. All time slots are initiated by the
master driving the data line low. The falling edge of the data line synchronizes the DS2423 to the master
by triggering a delay circuit in the DS2423. During write time slots, the delay circuit determines when the
DS2423 will sample the data line. For a read data time slot, if a “0” is to be transmitted, the delay circuit
determines how long the DS2423 will hold the data line low overriding the 1 generated by the master. If
the data bit is a “1”, the device will leave the read data time slot unchanged.
INITIALIZATION PROCEDURE “RESET AND PRESENCE PULSES”
Figure 10
DS2423
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PDF描述 |
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| DS2430A | The CAT24FC02 is a 2-kb Serial CMOS EEPROM internally organized as 256 words of 8 bits each |
| DS2430 | The CAT24FC02 is a 2-kb Serial CMOS EEPROM internally organized as 256 words of 8 bits each |
| DS2430AP | The CAT24FC02 is a 2-kb Serial CMOS EEPROM internally organized as 256 words of 8 bits each |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| DS243 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Analog IC |
| DS2430 | 制造商:DALLAS 制造商全稱:Dallas Semiconductor 功能描述:256-Bit 1-Wire EEPROM |
| DS2430A | 功能描述:電可擦除可編程只讀存儲(chǔ)器 RoHS:否 制造商:Atmel 存儲(chǔ)容量:2 Kbit 組織:256 B x 8 數(shù)據(jù)保留:100 yr 最大時(shí)鐘頻率:1000 KHz 最大工作電流:6 uA 工作電源電壓:1.7 V to 5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:SOIC-8 |
| DS2430A R | 制造商:MAXIM 制造商全稱:Maxim Integrated Products 功能描述:256-Bit 1-Wire EEPROM |
| DS2430A T | 制造商:MAXIM 制造商全稱:Maxim Integrated Products 功能描述:256-Bit 1-Wire EEPROM |
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