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參數(shù)資料
| 型號(hào)： | DS2423 |
| 廠商： | MAXIM INTEGRATED PRODUCTS INC |
| 元件分類： | DRAM |
| 英文描述： | 4K-Bit 1-Wire RAM with Counters(帶計(jì)數(shù)器的4K位1線串行RAM) |
| 中文描述： | 4K X 1 STANDARD SRAM, PDSO6 |
| 封裝： | 3.70 X 4 X 1.50 MM, TSOC-6 |
| 文件頁數(shù)： | 19/23頁 |
| 文件大小： | 146K |
| 代理商： | DS2423 |
DS2422/DS2423
021998 19/23
READ/WRITE TIMING DIAGRAM
Figure 11 cont’d
Read–data Time Slot
V
V
PULPULLUP
IH MIN
V
IL MAX
0V
t
SLOT
t
REC
t
RDV
t
LOWR
Regular Speed
60
μ
s < t
SLOT
< 120
μ
s
1
μ
s < t
LOWR
< 15
μ
s
0 < t
RELEASE
< 45
μ
s
1
μ
s < t
REC
<
t
RDV
= 15
μ
s
t
SU
< 1
μ
s
t
RELEASE
MASTER SAMPLING
WINDOW
RESISTOR
MASTER
DS242X
Overdrive Speed
6
μ
s < t
SLOT
< 16
μ
s
1
μ
s < t
LOWR
< 2
μ
s
0 < t
RELEASE
< 4
μ
s
1
μ
s < t
REC
<
t
RDV
= 2
μ
s
t
SU
< 1
μ
s
t
SU
CRC GENERATION
With the DS242X there are two different types of CRCs
(Cyclic Redundancy Checks). One CRC is an 8–bit
type and is stored in the most significant byte of the
64–bit ROM. The bus master can compute a CRC value
from the first 56 bits of the 64–bit ROM and compare it to
the value stored within the DS242X to determine if the
ROM data has been received error–free by the bus
master. The equivalent polynomial function of this CRC
is: X
8
+ X
5
+ X
4
+ 1. This 8–bit CRC is received in the
true (non–inverted) form when reading the ROM of the
DS242X. It is computed at the factory and lasered into
the ROM.
The other CRC is a 16–bit type, generated according to
the standardized CRC16–polynomial function x
16
+ x
15
+ x
2
+ 1. This CRC is used for error detection when
reading Data Memory using the Read Memory +
Counter command and for fast verification of a data
transfer when writing to the scratchpad. It is the same
type of CRC as is used with NVRAM based iButtons for
error detection within the iButton Extended File Struc-
ture. In contrast to the 8–bit CRC, the 16–bit CRC is
always returned or sent in the complemented (inverted)
form. A CRC–generator inside the DS242X chip (Figure
12) will calculate a new 16–bit CRC as shown in the
command flow chart of Figure 7. The bus master
compares the CRC value read from the device to the
one it calculates from the data and decides whether to
continue with an operation or re–read the portion of the
data with the CRC error.
With the initial pass through the Read Memory +
Counter flow chart the 16–bit CRC value is the result of
shifting the command byte into the cleared CRC gener-
ator, followed by the two address bytes, data bytes,
value of the counter associated with the page and zero
bits. Subsequent passes through the Read Memory +
Counter flow chart will generate a 16–bit CRC that is the
result of clearing the CRC generator and then shifting in
the data bytes, the value of the counter and the zero bits.
With the Write Scratchpad command the CRC is gener-
ated by first clearing the CRC generator and then shift-
ing in the command code, the Target Addresses TA1
and TA2 and all the data bytes. The DS242X will trans-
mit this CRC only if the data bytes written to the scratch-
pad include scratchpad ending offset 11111b. The data
may start at any location within the scratchpad.
For more details on generating CRC values including
example implementations in both hardware and soft-
ware, see the Book of DS19xx iButton Standards.
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相關(guān)代理商/技術(shù)參數(shù) |
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| DS2423D/T&R | 制造商:Maxim Integrated Products 功能描述:IC SRAM 4KBIT 6FLIPCHIP |
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| DS2423MRAB0 | 制造商:Thomas & Betts 功能描述:300A,NLT,3P4W,MG,423,3P480V |
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