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參數(shù)資料
| 型號(hào)： | DS2417X |
| 英文描述： | 1-Wire Time Chip With Interrupt |
| 中文描述： | 1 - Wire時(shí)鐘芯片，帶有中斷 |
| 文件頁(yè)數(shù)： | 10/15頁(yè) |
| 文件大?。?/td> | 260K |
| 代理商： | DS2417X |
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DS2417
10 of 15
1–WIRE SIGNALING
The DS2417 requires strict protocols to ensure data integrity. The protocol consists of four types of sig-
naling on one line: Reset Sequence with Reset Pulse and Presence Pulse, Write 0, Write 1 and Read Data.
Except for the presence pulse the bus master initiates all these signals.
The initialization sequence required to begin any communication with the DS2417 is shown in Figure 8.
A reset pulse followed by a presence pulse indicates the DS2417 is ready to send or receive data. The bus
master transmits (TX) a reset pulse (t
RSTL
, minimum 480
μ
s). The bus master then releases the line and
goes into receive mode (RX). The 1-Wire bus is pulled to a high state via the pullup resistor. After
detecting the rising edge on the data line, the DS2417 waits (t
PDH
, 15-60
μ
s) and then transmits the
presence pulse (t
PDL
, 60-240
μ
s).
INITIALIZATION PROCEDURE “RESET AND PRESENCE PULSES”
Figure 8
MASTER TX
"RESET PULSE"
V
PULLUP
V
PULLUP MIN
V
IH MIN
RESISTOR
MASTER
DS2417
MASTER RX "PRESENCE PULSE"
480 μs
≤
t
RSTL
<
∞
*
480 μs
≤
t
RSTH
<
∞
**
15 μs
≤
t
PDH
< 60 μs
60
≤
t
PDL
< 240 μs
V
IL MAX
0V
t
RSTH
t
RSTL
t
PDH
t
PDL
t
R
*
In order not to mask interrupt signaling by other devices on the 1-Wire bus t
RSTL
+ t
R
should al-
ways be less than 960 μs.
Includes recovery time
**
READ/WRITE TIME SLOTS
The definitions of write and read time slots are illustrated in Figure 9. The master initiates all time slots
by driving the data line low. The falling edge of the data line synchronizes the DS2417 to the master by
triggering an internal delay circuit. During write time slots, the delay circuit determines when the
DS2417 will sample the data line. For a read data time slot, if a “0” is to be transmitted, the delay circuit
determines how long the DS2417 will hold the data line low. If the data bit is a “1”, the DS2417 will not
hold the data line low at all.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| DS2417 | 1-Wire Time Chip With Interrupt |
| DS2417P | 1-Wire Time Chip With Interrupt |
| DS2417V | 1-Wire Time Chip With Interrupt |
| DS2423 | 4kbit 1-Wire RAM with Counter |
| DS2423P | 4kbit 1-Wire RAM with Counter |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| DS2417X/T&R | 制造商:Maxim Integrated Products 功能描述:IC TIMECHIP W/INTRPT 1WIRE CSP |
| DS2417X/T&R | 功能描述:IC TIMECHIP W/INTRPT 1WIRE CSP RoHS:否 類別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 實(shí)時(shí)時(shí)鐘 系列:- 產(chǎn)品培訓(xùn)模塊:Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:1 系列:- 類型:時(shí)鐘/日歷 特點(diǎn):警報(bào)器，閏年，SRAM 存儲(chǔ)容量:- 時(shí)間格式:HH:MM:SS（12/24 小時(shí)） 數(shù)據(jù)格式:YY-MM-DD-dd 接口:SPI 電源電壓:2 V ~ 5.5 V 電壓 - 電源，電池:- 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:8-WDFN 裸露焊盤 供應(yīng)商設(shè)備封裝:8-TDFN EP 包裝:管件 |
| DS2421FP000 | 制造商:Thomas & Betts 功能描述:200A,CON,3P4W,MG,421,3P440V |
| DS2421FR000 | 制造商:Thomas & Betts 功能描述:200A,REC,3P4W,MG,421,3P440V |
| DS2421FRA00 | 制造商:Thomas & Betts 功能描述:200A,REC,3P4W,MG,421,AGL,3P440V |
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