參數(shù)資料
型號(hào): DS2411R+T&R
廠商: Maxim Integrated Products
文件頁數(shù): 11/12頁
文件大小: 0K
描述: IC SILICON SERIAL NUMBER SOT-23
產(chǎn)品培訓(xùn)模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝: 1
類型: 硅序列號(hào)
應(yīng)用: PCB,網(wǎng)絡(luò)節(jié)點(diǎn),設(shè)備識(shí)別/注冊(cè)
安裝類型: 表面貼裝
封裝/外殼: TO-236-3,SC-59,SOT-23-3
供應(yīng)商設(shè)備封裝: SOT-23-3
包裝: 標(biāo)準(zhǔn)包裝
產(chǎn)品目錄頁面: 1429 (CN2011-ZH PDF)
其它名稱: DS2411R+DKR
DS2411
8 of 12
1-WIRE SIGNALING
The DS2411 requires strict protocols to ensure data integrity. The protocol consists of four types of
signaling on one line: Reset Sequence with Reset Pulse and Presence Pulse, Write 0, Write 1, and Read
Data. Except for the presence pulse the bus master initiates all these signals. The DS2411 can
communicate at two different speeds: standard speed and Overdrive speed. If not explicitly set into the
Overdrive mode, the DS2411 will communicate at standard speed. While in Overdrive Mode the fast
timing applies to all waveforms.
To get from idle to active, the voltage on the 1-Wire line needs to fall from VPUP below the threshold VTL.
To get from active to idle, the voltage needs to rise from VILMAX past the threshold VTH. The voltage
VILMAX is relevant for the DS2411 when determining a logical level, but not for triggering any events.
The initialization sequence required to begin any communication with the DS2411 is shown in Figure 6.
A Reset Pulse followed by a Presence Pulse indicates the DS2411 is ready to receive data, given the
correct ROM and memory function command. In a mixed population network, the reset low time tRSTL
needs to be long enough for the slowest 1-Wire slave device to recognize it as a reset pulse. If the bus
master uses slew-rate control on the falling edge, it must pull down the line for tRSTL + tF to compensate
for the edge. A tRSTL duration of 480s or longer will exit the Overdrive Mode returning the device to
standard speed. If the DS2411 is in Overdrive Mode and tRSTL is no longer than 80s, the device will
remain in Overdrive Mode.
After the bus master has released the line it goes into receive mode (RX). Now, the 1-Wire bus is pulled
to VPUP via the pullup resistor or, in case of a DS2480B driver, by active circuitry. When the threshold
VTH is crossed, the DS2411 waits for tPDH and then transmits a Presence Pulse by pulling the line low for
tPDL. To detect a presence pulse, the master must test the logical state of the 1-Wire line at tMSP.
The tRSTH window must be at least the sum of tPDHMAX, tPDLMAX, and tRECMIN. Immediately after tRSTH is
expired, the DS2411 is ready for data communication. In a mixed population network, tRSTH should be
extended to minimum 480s at standard speed and 48s at Overdrive speed to accommodate other 1-
Wire devices.
Read/Write Time Slots
Data communication with the DS2411 takes place in time slots that carry a single bit each. Write time
slots transport data from bus master to slave. Read time-slots transfer data from slave to master. The
definitions of the write and read time slots are illustrated in Figure 7.
All communication begins with the master pulling the data line low. As the voltage on the 1-Wire line
falls below the threshold VTL, the DS2411 starts its internal timing generator that determines when the
data line will be sampled during a write time slot and how long data will be valid during a read time slot.
Master to Slave
For a write-one time slot, the voltage on the data line must have crossed the VTHMAX threshold after the
write-one low time tW1LMAX is expired. For a write-zero time slot, the voltage on the data line must stay
below the VTHMIN threshold until the write-zero low time tW0LMIN is expired. For most reliable
communication the voltage on the data line should not exceed VILMAX during the entire tW0L window.
After the VTHMAX threshold has been crossed, the DS2411 needs a recovery time tREC before it is ready for
the next time slot.
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