參數(shù)資料
型號(hào): DS2407T
英文描述: Dual Addressable Switch Plus 1K.Bit Memory
中文描述: 雙尋址開(kāi)關(guān)與1K.Bit記憶
文件頁(yè)數(shù): 24/31頁(yè)
文件大小: 194K
代理商: DS2407T
DS2407
012099 24/31
INITIALIZATION PROCEDURE “RESET AND PRESENCE PULSES”
Figure 14
t
RSTH
t
RSTL
t
R
V
PULLUP
V
PULLUP MIN
IH MIN
V
IL MAX
0V
t
PDH
t
PDL
RESISTOR
MASTER
DS2407
MASTER R
X
“PRESENCE PULSE”
MASTER T
X
“RESET PULSE”
480
μ
s < t
RSTL
<
480
μ
s < t
RSTH
<
15
μ
s < t
PDH
< 60
μ
s
60
μ
s < t
PDL
< 240
μ
s
*
(includes recovery time)
* In order not to mask interrupt signalling by other devices on the 1–Wire bus, t
RSTL
+ t
R
should always be less than
960
μ
s. t
RSTL
should be limited to maximum 5 ms. Otherwise the DS2407 may perform a power–on reset cycle.
READ/WRITE TIMING DIAGRAM
Figure 15
Write–one Time Slot
60
μ
s
t
REC
t
LOW1
V
PULLUP
V
PULLUP MIN
V
IH MIN
V
IL MAX
0V
15
μ
s
DS2407
SAMPLING WINDOW
t
SLOT
RESISTOR
MASTER
DS2407
60
μ
s < t
SLOT
< 120
μ
s
1
μ
s < t
LOW1
< 15
μ
s
1
μ
s < t
REC
<
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