參數(shù)資料
型號(hào): DS2405P
廠商: DALLAS SEMICONDUCTOR
元件分類: Memory IC:Other
英文描述: SPECIALTY MEMORY CIRCUIT, PDSO6
封裝: TSOC-6
文件頁(yè)數(shù): 3/15頁(yè)
文件大?。?/td> 236K
代理商: DS2405P
DS2405
11 of 15
102299
Skip ROM [CCh]
The complete 1-Wire protocol for all Dallas Semiconductor iButtons contains a Skip ROM command.
Since the DS2405 contains only the 64-bit ROM with no additional data fields, the Skip ROM is not
applicable and will cause no further activity on the 1-Wire bus if executed. The DS2405 does not interfere
with other 1-Wire parts on a multidrop bus that do respond to a Skip ROM (for example, a DS2405 and
DS1994 on the same bus).
1-WIRE SIGNALING
The DS2405 requires strict protocols to ensure data integrity. The protocol consists of four types of
signaling on one line: reset sequence with Reset Pulse and Presence Pulse, write 0, write 1 and read data.
All these signals except Presence Pulse are initiated by the bus master.
The initialization sequence required to begin any communication with the DS2405 is shown in Figure 5.
A Reset Pulse followed by a Presence Pulse indicates the DS2405 is ready to send or receive data given
the correct ROM command.
The bus master transmits (TX) a Reset Pulse (tRSTL, minimum 480
s). The bus master then releases the
line and goes into receive mode (RX). The 1-Wire bus is pulled to a high state via the 5 k
pullup
resistor. After detecting the rising edge on the data pin, the DS2405 waits (tPDH, 15-60
s) and then
transmits the Presence Pulse (tPDL, 60-240
s).
INITIALIZATION PROCEDURE “RESET AND PRESENCE PULSES” Figure 5
480
s ≤t
RSTL <
∞*
480
s ≤t
RSTH <
∞ (includes recovery time)
15
s ≤t
PDH < 60
s
60
s ≤t
PDL < 240
s
In order not to mask interrupt signaling by other devices on the 1-Wire bus, t
RSTL + tR should always
be less than 960
s.
RESISTOR
MASTER
DS2405
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