- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄97868 > DS2405 (MAXIM INTEGRATED PRODUCTS INC) SPECIALTY MEMORY CIRCUIT, PBCY3 PDF資料下載
參數(shù)資料
| 型號(hào)： | DS2405 |
| 廠商： | MAXIM INTEGRATED PRODUCTS INC |
| 元件分類： | Memory IC:Other |
| 英文描述： | SPECIALTY MEMORY CIRCUIT, PBCY3 |
| 封裝： | TO-92, 3 PIN |
| 文件頁(yè)數(shù)： | 7/15頁(yè) |
| 文件大?。?/td> | 429K |
| 代理商： | DS2405 |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)當(dāng)前第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)
DS2405
15 of 15
NOTES:
1. All voltages are referenced to ground.
2. VPUP = external pullup voltage.
3. Input load is to ground.
4. An additional reset or communication sequence cannot begin until the reset high time has expired.
5. Read data setup time refers to the time the host must pull the 1-Wire bus low to read a bit. Data is
guaranteed to be valid within 1
μs of this falling edge and will remain valid for 14μs minimum (15μs
total from falling edge on 1-Wire bus).
6. VIH is a function of the external pull-up resistor and the VCC supply.
7. Capacitance on the data pin could be 800pF when power is first applied. If a 5k
Ω resistor is used to
pull-up the data line to VCC, 5μs after power has been applied the parasite capacitance will not affect
normal communications.
8. VIH for PIO pin should always be greater than or equal to VPUP -0.3V.
9. Input resistance is to ground.
10. Under certain low voltage conditions VILMAX may have to be reduced to as much as 0.5V to always
guarantee a Presence Pulse.
11. The optimal sampling point for the master is as close as possible to the end of the 15μs tRDV period
without exceeding tRDV. For the case of a Read 1 time slot, this maximizes the amount of time for the
pull-up resistor to recover the line to a high level. For a Read 0 time slot, it ensures that a read will
occur before the fastest 1-Wire device(s) release the line.
12. The duration of the low pulse sent by the master should be a minimum of 1μs with a maximum value
as short as possible to allow time for the pull-up resistor to recover the line to a high level before the
1-Wire device samples in the case of a Write 1 Low Time, or before the master samples in the case of
a Read Low Time.
13. The Reset Low Time (tRSTL) should be restricted to a maximum of 960μs to allow interrupt signaling;
otherwise, it could mask or conceal interrupt pulses.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| DS2405Z | SPECIALTY MEMORY CIRCUIT, PDSO4 |
| DS2406P | 1K X 1 OTPROM, PDSO6 |
| DS2406 | 1K X 1 OTPROM, PBCY3 |
| DS2406X | 1K X 1 OTPROM |
| DS2409P | SPECIALTY TELECOM CIRCUIT, PDSO6 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| DS2405/R | 制造商:DALLAS 制造商全稱:Dallas Semiconductor 功能描述:Addressable Switch |
| DS2405/T | 制造商:DALLAS 制造商全稱:Dallas Semiconductor 功能描述:Addressable Switch |
| DS2405/T&R | 功能描述:接口 - 專用 RoHS:否 制造商:Texas Instruments 產(chǎn)品類型:1080p60 Image Sensor Receiver 工作電源電壓:1.8 V 電源電流:89 mA 最大功率耗散: 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:BGA-59 |
| DS2405/TR | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Peripheral IC |
| DS2405_07 | 制造商:DALLAS 制造商全稱:Dallas Semiconductor 功能描述:Addressable Switch |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。