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參數(shù)資料
| 型號： | DS2404S |
| 英文描述： | EconoRAM Time Chip |
| 中文描述： | EconoRAM時鐘芯片 |
| 文件頁數(shù)： | 21/28頁 |
| 文件大?。?/td> | 663K |
| 代理商： | DS2404S |
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DS2404
21 of 28
020998
TYPE 2 INTERRUPT (SPECIAL CASE)
Figure 15
3-WIRE I/O COMMUNICATIONS
The 3–wire bus is comprised of three signals. These are the
RST
(reset) signal, the CLK (clock) signal,
and the DQ (data) signal. All data transfers are initiated by driving the
RST
input high. Driving the RST
input low terminates communication. (See Figures 19 and 20.)
A clock cycle is a sequence of a falling edge followed by a rising edge. For data inputs, the data must be
valid during the rising edge of a clock cycle. Command bits and data bits are input on the rising edge of
the clock and data bits are output on the falling edge of the clock. When reading data from the DS2404,
the DQ pin goes to a high impedance state while the clock is high. Taking
RST
low will terminate any
communication and cause the DQ pin to go to a high impedance state.
POWER CONTROL
There are two methods of supplying power to the DS2404, V
CC
Operate mode with battery backup and
Battery Operate mode. If the DS2404 is used in an application where battery backup is not desired, the
part must be wired for Battery Operate mode.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| DS2405 | Addressable Switch |
| DS2405P | Addressable Switch |
| DS2405T | Addressable Switch |
| DS2405V | Addressable Switch |
| DS2405Y | Addressable Switch |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| DS2404S-001 | 制造商:Maxim Integrated Products 功能描述:ECONORAM/TIME, SOIC16 (GENERIC) - Rail/Tube |
| DS2404S-001/T&R | 制造商:Maxim Integrated Products 功能描述:ECONORAM/TIME, SOIC16-TRL (GENERIC) - Tape and Reel |
| DS2404S-001+ | 制造商:Maxim Integrated Products 功能描述:REAL TIME CLOCK SERL 512BYTE 16SOIC - Rail/Tube |
| DS2404S-001+T&R | 制造商:Maxim Integrated Products 功能描述:REAL TIME CLOCK SERL 512BYTE 16SOIC - Tape and Reel |
| DS2404S-C01 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Peripheral IC |
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