參數(shù)資料
型號: DS232AS-N
廠商: DALLAS SEMICONDUCTOR
元件分類: Line Driver or Receiver
英文描述: LINE TRANSCEIVER, PDSO16
封裝: 0.300 INCH, SOIC-16
文件頁數(shù): 9/23頁
文件大小: 409K
代理商: DS232AS-N
MAX15026
Low-Cost, Small, 4.5V to 28V Wide Operating
Range, DC-DC Synchronous Buck Controller
17
Maxim Integrated
The gain of the error amplifier (GAINEA) in midband fre-
quencies is:
GAINEA = 2
π x fO x C1 x RF
The total loop gain as the product of the modulator gain
and the error amplifier gain at fO is 1.
So:
Solving for CI:
3) Use the second pole (fP2) to cancel fZO when fPO <
fO < fZO < fSW/2. The frequency response of the
loop gain does not flatten out soon after the 0dB
crossover, and maintains a -20dB/decade slope up
to 1/2 of the switching frequency. This is likely to
occur if the output capacitor is a low-ESR tantalum.
Set fP2 = fZO.
When using a ceramic capacitor, the capacitor ESR
zero fZO is likely to be located even above 1/2 the
switching frequency, fPO < fO < fSW/2 < fZO. In this
case, place the frequency of the second pole (fP2) high
enough to not significantly erode the phase margin at
the crossover frequency. For example, set fP2 at 5 x fO
so that the contribution to phase loss at the crossover
frequency fO is only about 11°:
fP2 = 5 x fPO
Once fP2 is known, calculate RI:
4) Place the second zero (fZ2) at 0.2 x fO or at fPO,
whichever is lower, and calculate R1 using the fol-
lowing equation:
5) Place the third pole (fP3) at 1/2 the switching fre-
quency and calculate CCF:
6) Calculate R2 as:
MOSFET Selection
The MAX15026 step-down controller drives two external
logic-level n-channel MOSFETs. The key selection
parameters to choose these MOSFETs include:
On-Resistance (RDS(ON))
Maximum Drain-to-Source Voltage (VDS(MAX))
Minimum Threshold Voltage (VTH(MIN))
Total Gate Charge (QG)
Reverse Transfer Capacitance (CRSS)
Power Dissipation
The two n-channel MOSFETs must be a logic-level type
with guaranteed on-resistance specifications at VGS =
4.5V. For maximum efficiency, choose a high-side
MOSFET that has conduction losses equal to the
switching losses at the typical input voltage. Ensure
that the conduction losses at minimum input voltage do
not exceed the MOSFET package thermal limits, or vio-
late the overall thermal budget. Also, ensure that the
conduction losses plus switching losses at the maxi-
mum input voltage do not exceed package ratings or
violate the overall thermal budget. Ensure that the DL
gate driver can drive the low-side MOSFET. In particu-
lar, check that the dv/dt caused by the high-side
MOSFET turning on does not pull up the low-side
MOSFET gate through the drain-to-gate capacitance
of the low-side MOSFET, which is the most frequent
cause of cross-conduction problems.
Check power dissipation when using the internal linear
regulator to power the gate drivers. Select MOSFETs
with low gate charge so that VCC can power both dri-
vers without overheating the device.
PDRIVE = VCC x QG_TOTAL x fSW
where QG_TOTAL is the sum of the gate charges of the
two external MOSFETs.
R
V
VV
R
FB
OUT
FB
21
C
fR
C
CF
F
SW
F
=
××
×
()
20 5
1
π
.
R
fC
R
ZI
I
1
2
1
2
=
××
π
R
fC
I
PI
=
××
1
2
π
C
Vf
L
C
VR
I
RAMP
O
OUT
IN
F
=
××
×
()
×
2
π
V
fC
L
IN
RAMP
OOUT
OUT
×
××
×
1
2
()
π
GAIN
MOD
EA
×= 1
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