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參數(shù)資料
| 型號(hào)： | DS2251T |
| 廠商： | MAXIM INTEGRATED PRODUCTS INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 128K Soft Microcontroller Module(128K軟件微控制器模塊) |
| 中文描述： | 8-BIT, MICROCONTROLLER, SMA72 |
| 文件頁(yè)數(shù)： | 5/20頁(yè) |
| 文件大?。?/td> | 156K |
| 代理商： | DS2251T |
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DS2251T
021998 5/20
PIN
DESCRIPTION
9
RST –
Active high reset input. A logic 1 applied to this pin will activate a reset state. This pin is
pulled down internally, can be left unconnected if not used. An RC power–on reset circuit is not
needed and is NOT recommended.
29
PSEN –
Program Store Enable. This active low signal is used to enable an external program
memory when using the Expanded bus. It is normally an output and should be unconnected if
not used.
30
ALE –
Address Latch Enable. Used to de–multiplex the multiplexed Expanded Address/Data bus
on Port 0. This pin is normally connected to the clock input on a ‘373 type transparent latch.
19, 18
XTAL2, XTAL1.
Used to connect an external crystal to the internal oscillator. XTAL1 is the input
to an inverting amplifier and XTAL2 is the output.
20
GND –
Logic ground.
40
V
CC
–
+5V
.
72
BA15 –
Monitor test point to reflect the logical value of A15. Not needed for memory access.
54–41
BA13 – 0.
Byte–wide Address bus bits 13–0. This bus is combined with the non–multiplexed data
bus (BD7–0) to access on–board NV SRAM and off–board peripherals. Peripheral decoding is
performed using PE3 and PE4. These are on 16K boundaries, so BA14 or BA15 are not needed.
Read/write access is controlled by R/W. BA13–0 connect directly to memory mapped
peripherals.
63–56
BD7 – 0.
Byte–wide Data bus bits 7–0. This 8–bit bi–directional bus is combined with the non–
multiplexed address bus (BA14–0) to access on–board NV SRAM and off–board peripherals.
64
R/W –
Read/Write. This signal provides the write enable to the SRAMs on the Byte–wide bus.
It is controlled by the memory map and Partition. The blocks selected as Program (ROM) will be
write protected. This signal is also used for the write enable to off–board peripherals.
66
PE3 –
Peripheral Enable 3. Accesses data memory between addresses 8000h and BFFFh when
the PES bit is set to a logic 1. PE3 is not lithium backed and can be connected to any type of
peripheral function.
67
PE4 –
Peripheral Enable 4. Accesses data memory between addresses C000h and FFFFh when
the PES bit is set to a logic 1. PE4 is not lithium backed and can be connected to any type of
peripheral function.
31
PROG –
Invokes the Bootstrap loader on a falling edge. This signal should be debounced so that
only one edge is detected. If connected to ground, the micro will enter Bootstrap loading on pow-
er–up. This signal is pulled up internally.
71
VRST –
This I/O pin (open–drain with internal pull–up) indicates that the power supply (V
CC
) has
fallen below the V
level and the micro is in a reset state. When this occurs, the DS2251T
will drive this pin to a logic 0. Because the micro is lithium backed, this signal is guaranteed even
when V
CC
=0V. Because it is an I/O pin, it will also force a reset if pulled low externally. This allows
multiple parts to synchronize their power–down resets.
65
PF –
This output goes to a logic 0 to indicate that the micro has switched to lithium backup. It
corresponds to V
CC
< V
LI
. Because the micro is lithium backed, this signal is guaranteed even
when V
CC
=0V.
55
INTB –
INTB from the real time clock. This output may be connected to a micro interrupt
input.
68
INTP –
INTP from the real time clock. This open–drain output requires a pull–up and may
beconnected to a micro interrupt input.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| DS2251T_06 | 制造商:DALLAS 制造商全稱:Dallas Semiconductor 功能描述:128k Soft Microcontroller Module |
| DS2251T08-08 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Microcontroller |
| DS2251T08-12 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Microcontroller |
| DS2251T08-16 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Microcontroller |
| DS2251T128-08 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Microcontroller |
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