參數(shù)資料
型號: DS2229
廠商: DALLAS SEMICONDUCTOR
元件分類: Static RAM
英文描述: 512K X 16 MULTI DEVICE SRAM MODULE, 85 ns, SMA80
封裝: SIMM-80
文件頁數(shù): 10/10頁
文件大?。?/td> 374K
代理商: DS2229
DS2229
9 of 10
WRITE CYCLE 2 Figure 7
NOTES:
1. A write occurs during the overlap of a low CE0 - CE3 , a high CS, and a low WE . A write begins at the
latest transition among CE0 - CE3 going low, CS going high, and WE going low. A write ends at the
earliest transition among CE0 - CE3 going high, CS going low and WE going high. tWP is measured
from the beginning of write to the end of write.
2.
WE
is high for a read cycle.
3. tDS ends and tDH begins at the earliest transaction among CE0 - CE3 going high.
4. tWR is measured from the earliest of CE0 - CE3 or WE going high or CS going low to the end of write
cycle.
5. CS controls address buffer, WE buffer, CE0 - CE3 buffer, OE buffer and DIN buffer. If CS controls
data retention mode, VIN levels (address, WE , OE , CE0 - CE3 , I/O) can be in the high impedance state.
If CE0 - CE3 controls data retention mode, CS must be CS
≥ V
CC - 0.2V or 0V < CS < 0.2V. The other
input levels (address, WE , OE , I/O) can be in the high impedance state.
6. If CE0 - CE3 goes low simultaneously with WE going low or after WE going low, the outputs remain
in a high impedance state.
7. If CE0 - CE3 is low and CS is high during this period, I/O pins are in the output state. Therefore, the
input signals of the opposite phase to the outputs must not be applied to them.
8. This parameter is sampled and not 100% tested.
9. Only one CE active during any read or write cycle.
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