參數(shù)資料
型號: DS21Q59L+
廠商: Maxim Integrated Products
文件頁數(shù): 48/76頁
文件大小: 0K
描述: IC TXRX E1 QUAD 3.3V 100LQFP
產(chǎn)品培訓(xùn)模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標準包裝: 90
功能: 收發(fā)器
接口: E1
電路數(shù): 4
電源電壓: 3.14 V ~ 3.47 V
電流 - 電源: 230mA
工作溫度: 0°C ~ 70°C
安裝類型: 表面貼裝
封裝/外殼: 100-LQFP
供應(yīng)商設(shè)備封裝: 100-LQFP(14x14)
包裝: 托盤
包括: AIS 警報檢測器和發(fā)生器,回送功能,PRBS 發(fā)生器 / 檢測器,遠程檢測器和發(fā)生器
產(chǎn)品目錄頁面: 1429 (CN2011-ZH PDF)
DS21Q59 Quad E1 Transceiver
52 of 76
22.
CODE MARK INVERSION (CMI)
The DS21Q59 provides a CMI interface for connecting to optical transports. This interface is a unipolar 1T2B-
coded signal. Ones are alternately encoded as a logical 1 or 0 level for the full duration of the clock period. Zeros
are encoded as a 0-to-1 transition at the middle of the clock period. Figure 22-1 shows an example data pattern
and its CMI result. The control bit for enabling CMI is in the OUTAC register, as shown below.
Register Name:
OUTAC
Register Description:
OUTA Control Register
Register Address:
1A Hex
Bit #
7
6
5
4
3
2
1
0
Name
TTLIE
CMII
CMIE
OA4
OA3
OA2
OA1
OA0
NAME
BIT
FUNCTION
TTLIE
7
TTL Input Enable. When this bit is set, the receiver can accept TTL
positive and negative data at the RTIP and RRING inputs. The data is
clocked in on the falling edge of MCLK.
CMII
6
CMI Invert
0 = CMI input data not inverted
1 = CMI input data inverted
CMIE
5
Transmit and Receive CMI Enable
0 = Transmit and receive line interface operates in normal AMI/HDB3 mode
1 = Transmit and receive line interface operate in CMI mode. TTIP is CMI
output and RTIP is CMI input. In this mode of operation TRING and RRING
are no connects.
OA4
4
OUTA Control Bit 4. Inverts OUTA output.
OA3
3
OUTA Control Bit 3. See Table 20-A for details.
OA2
2
OUTA Control Bit 2. See Table 20-A for details.
OA1
1
OUTA Control Bit 1. See Table 20-A for details.
OA0
0
OUTA Control Bit 0. See Table 20-A for details.
Figure 22-1. CMI Coding
0
1
0
1
CLOCK
DATA
CMI
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