參數(shù)資料
型號(hào)： DS21Q554N
廠商： Maxim Integrated Products
文件頁(yè)數(shù)： 12/13頁(yè)
文件大?。?/td> 0K
描述： IC TRANSCEIVER E1 QUAD 5V 256BGA
產(chǎn)品培訓(xùn)模塊： Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝： 40
功能： 收發(fā)器
接口： E1
電路數(shù)： 4
電源電壓： 5V
安裝類型： 表面貼裝
封裝/外殼： 256-BBGA
供應(yīng)商設(shè)備封裝： 256-BGA（27x27）
包裝： 托盤
包括： 警報(bào)檢測(cè)和生成，通道控制，調(diào)幀器，HDLC 控制器
DALLAS SEMICONDUCTOR
DS21Q352/DS21Q552/DS21Q354/DS21Q554 Preliminary Data Sheet
December 29, 1998
8
H2
RLOS/LOTC1
O
Receive Loss Of Sync / Loss Of Transmit Clock for SCT1.
E17
RLOS/LOTC2
O
Receive Loss Of Sync / Loss Of Transmit Clock for SCT2.
E1
RLOS/LOTC3
O
Receive Loss Of Sync / Loss Of Transmit Clock for SCT3.
V11
RLOS/LOTC4
O
Receive Loss Of Sync / Loss Of Transmit Clock for SCT4.
L1
RMSYNC1
O
Receive Multiframe Sync for SCT1.
D16
RMSYNC2
O
Receive Multiframe Sync for SCT2.
F2
RMSYNC3
O
Receive Multiframe Sync for SCT3.
W16
RMSYNC4
O
Receive Multiframe Sync for SCT4.
R3
RNEGI1
I
Receive Negative Data for the Framer on SCT1.
D13
RNEGI2
I
Receive Negative Data for the Framer on SCT2.
A1
RNEGI3
I
Receive Negative Data for the Framer on SCT3.
P17
RNEGI4
I
Receive Negative Data for the Framer on SCT4.
L3
RNEGO1
O
Receive Negative Data from the LIU on SCT1.
B15
RNEGO2
O
Receive Negative Data from the LIU on SCT2.
C2
RNEGO3
O
Receive Negative Data from the LIU on SCT3.
U17
RNEGO4
O
Receive Negative Data from the LIU on SCT4.
R4
RPOSI1
I
Receive Positive Data for the Framer on SCT1.
B14
RPOSI2
I
Receive Positive Data for the Framer on SCT2.
B2
RPOSI3
I
Receive Positive Data for the Framer on SCT3.
V15
RPOSI4
I
Receive Positive Data for the Framer on SCT4.
L4
RPOSO1
O
Receive Positive Data from the LIU on SCT1.
A16
RPOSO2
O
Receive Positive Data from the LIU on SCT2.
B1
RPOSO3
O
Receive Positive Data from the LIU on SCT3.
U15
RPOSO4
O
Receive Positive Data from the LIU on SCT4.
Y11
RRING1
I
Receive Analog Ring Input for SCT1.
Y14
RRING2
I
Receive Analog Ring Input for SCT2.
Y17
RRING3
I
Receive Analog Ring Input for SCT3.
Y20
RRING4
I
Receive Analog Ring Input for SCT4.
J2
RSER1
O
Receive Serial Data for SCT1.
D15
RSER2
O
Receive Serial Data for SCT2.
E2
RSER3
O
Receive Serial Data for SCT3.
W17
RSER4
O
Receive Serial Data for SCT4.
L2
RSIG1
O
Receive Signaling Output for SCT1.
B16
RSIG2
O
Receive Signaling Output for SCT2.
C1
RSIG3
O
Receive Signaling Output for SCT3.
Y18
RSIG4
O
Receive Signaling Output for SCT4.
K1
RSIGF1
O
Receive Signaling Freeze Output for SCT1.
C15
RSIGF2
O
Receive Signaling Freeze Output for SCT2.
D2
RSIGF3
O
Receive Signaling Freeze Output for SCT3.
V16
RSIGF4
O
Receive Signaling Freeze Output for SCT4.
G1
RSYNC1
I/O
Receive Sync for SCT1.
D12
RSYNC2
I/O
Receive Sync for SCT2.
D1
RSYNC3
I/O
Receive Sync for SCT3.
V12
RSYNC4
I/O
Receive Sync for SCT4.
H1
RSYSCLK1
I
Receive System Clock for SCT1.
F17
RSYSCLK2
I
Receive System Clock for SCT2.
G3
RSYSCLK3
I
Receive System Clock for SCT3.
W14
RSYSCLK4
I
Receive System Clock for SCT4.
Y10
RTIP1
I
Receive Analog Tip Input for SCT1.
Y13
RTIP2
I
Receive Analog Tip Input for SCT2.
Y16
RTIP3
I
Receive Analog Tip Input for SCT3.
Y19
RTIP4
I
Receive Analog Tip Input for SCT4.
P1
RVDD1
–
Receive Analog Positive Supply.
J17
RVDD2
–
Receive Analog Positive Supply.
E4
RVDD3
–
Receive Analog Positive Supply.
W18
RVDD4
–
Receive Analog Positive Supply.
R2
RVSS1
–
Receive Analog Signal Ground
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