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參數(shù)資料
| 型號(hào)： | DS21Q41BT |
| 廠商： | DALLAS SEMICONDUCTOR |
| 元件分類： | Digital Transmission Controller |
| 英文描述： | DATACOM, FRAMER, PQFP128 |
| 封裝： | TQFP-128 |
| 文件頁數(shù)： | 32/61頁 |
| 文件大?。?/td> | 714K |
| 代理商： | DS21Q41BT |
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DS21Q41B
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Each of the bit positions in the Transmit Idle Registers (TIR1/TIR2/TIR3) represent a DS0 channel in the
outgoing frame. When these bits are set to a 1, the corresponding channel will transmit the Idle Code
contained in the Transmit Idle Definition Register (TIDR). Robbed bit signaling and Bit 7 stuffing will
occur over the programmed Idle Code unless the DS0 channel is made transparent by the Transmit
Transparency Registers.
9.0 CLOCK BLOCKING REGISTERS
The Receive Channel Blocking Registers (RCBR1/RCBR2/RCBR3) and the Transmit Channel Blocking
Registers (TCBR1/TCBR2/TCBR3) control the RCHBLK and TCHBLK pins respectively. The
RCHBLK and TCHCLK pins are user-programmable outputs that can be forced either high or low during
individual channels. These outputs can be used to block clocks to a USART or LAPD controller in
Fractional T1 or ISDN-PRI applications. When the appropriate bits are set to a 1, the RCHBLK and
TCHCLK pins will be held high during the entire corresponding channel time. See the timing in Section
12 for an example.
RCBR1/RCBR2/RCBR3:
RECEIVE CHANNEL BLOCKING REGISTERS (Address=6C to 6E Hex)
(MSB)
(LSB)
CH8
CH7
CH6
CH5
CH4
CH3
CH2
CH1
RCBR1 (6C)
CH16
CH15
CH14
CH13
CH12
CH11
CH10
CH9
RCBR2 (6D)
CH24
CH23
CH22
CH21
CH20
CH19
CH18
CH17
RCBR3 (6E)
SYMBOL
POSITION
NAME AND DESCRIPTION
CH24
RCBR3.7
Receive Channel Blocking Registers.
0=force the RCHBLK pin to remain low during this channel time
CH1
RCBR1.0
1=force the RCHBLK pin high during this channel time
TCBR1/TCBR2/TCBR3:
TRANSMIT CHANNEL BLOCKING REGISTERS (Address=32 to 34 Hex)
(MSB)
(LSB)
CH8
CH7
CH6
CH5
CH4
CH3
CH2
CH1
TCBR1 (32)
CH16
CH15
CH14
CH13
CH12
CH11
CH10
CH9
TCBR2 (33)
CH24
CH23
CH22
CH21
CH20
CH19
CH18
CH17
TCBR3 (34)
SYMBOL
POSITION
NAME AND DESCRIPTION
CH24
TCBR3.7
Transmit Channel Blocking Registers.
0=force the TCHBLK pin to remain low during this channel time
CH1
TCBR1.0
1=force the TCHBLK pin high during this channel time
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| DS21Q42TN | DATACOM, FRAMER, PQFP128 |
| DS21Q42T | DATACOM, FRAMER, PQFP128 |
| DS21Q43AT | DATACOM, FRAMER, PQFP128 |
| DS21Q44T | DATACOM, FRAMER, PQFP128 |
| DS21Q44TN | DATACOM, FRAMER, PQFP128 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| DS21Q41-BT | 制造商:Rochester Electronics LLC 功能描述: 制造商:Maxim Integrated Products 功能描述: |
| DS21Q41BT+ | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| DS21Q41BT+T | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| DS21Q41BTN | 制造商:DALLAS 制造商全稱:Dallas Semiconductor 功能描述:Quad T1 Framer |
| DS21Q41-BTN | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
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