參數(shù)資料
型號: DS21FT44N
廠商: MAXIM INTEGRATED PRODUCTS INC
元件分類: Digital Transmission Controller
英文描述: DATACOM, FRAMER, PBGA300
封裝: 27 X 27 MM, 1.27 MM PITCH, MCMBGA-300
文件頁數(shù): 97/117頁
文件大?。?/td> 691K
代理商: DS21FT44N
DS21FT44/DS21FF44
80 of 117
TDC1: TRANSMIT HDLC DS0 CONTROL REGISTER 1 (Address = BA Hex)
(MSB)
(LSB)
THE
TSaDS
TDS0M
TD4
TD3
TD2
TD1
TD0
SYMBOL
POSITION
NAME AND DESCRIPTION
THE
TDC1.7
Transmit HDLC Enable
0 = disable HDLC controller (no data inserted by HDLC
controller into the transmit data stream)
1 = enable HDLC controller to allow insertion of HDLC data
into either the Sa position or multiple DS0 channels as defined
by TDC1 (see bit definitions below)
TSaDS
TDC1.6
Transmit Sa Bit/DS0 Select. This bit is ignored if TDC1.7 is
set to zero.
0 = route Sa bits from the HDLC controller. TD0 to TD4
defines which Sa bits are to be routed. TD4 corresponds to
Sa4, TD3 to Sa5, TD2 to Sa6, TD1 to Sa7, and TD0 to Sa8.
1 = route DS0 channels from the HDLC controller. TDC1.5 is
used to determine how the DS0 channels are selected.
TDS0M
TDC1.5
DS0 Selection Mode
0 = use the TD0 to TD4 bits to select which single DS0
channel to use
1 = use the TCHBLK control registers to select which DS0
channels to use
TD4
TDC1.4
DS0 Channel Select Bit 4. MSB of the DS0 channel select.
TD3
TDC1.3
DS0 Channel Select Bit 3
TD2
TDC1.2
DS0 Channel Select Bit 2
TD1
TDC1.1
DS0 Channel Select Bit 1
TD0
TDC1.0
DS0 Channel Select Bit 0. LSB of the DS0 channel select.
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