參數(shù)資料
型號: DS21FT42N
廠商: Maxim Integrated Products
文件頁數(shù): 26/114頁
文件大?。?/td> 0K
描述: IC FRAMER T1 4X3 12CH IND 300BGA
產(chǎn)品培訓(xùn)模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標準包裝: 40
控制器類型: T1 調(diào)幀器
接口: 并行/串行
電源電壓: 2.97 V ~ 3.63 V
電流 - 電源: 225mA
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 300-BBGA
供應(yīng)商設(shè)備封裝: 300-PBGA(27x27)
包裝: 管件
DS21FT42/DS21FF42
19 of 114
TRANSMIT SIDE PINS
Signal Name:
TCLK
Signal Description:
Transmit Clock
Signal Type:
Input
A 1.544 MHz primary clock. Used to clock data through the transmit side formatter.
Signal Name:
TSER
Signal Description:
Transmit Serial Data
Signal Type:
Input
Transmit NRZ serial data. Sampled on the falling edge of TCLK when the transmit side elastic store is
disabled. Sampled on the falling edge of TSYSCLK when the transmit side elastic store is enabled.
Signal Name:
TCHCLK
Signal Description:
Transmit Channel Clock
Signal Type:
Output
A 192 kHz clock which pulses high during the LSB of each channel. Synchronous with TCLK when the
transmit side elastic store is disabled. Synchronous with TSYSCLK when the transmit side elastic store
is enabled. Useful for parallel to serial conversion of channel data. This function is available when FMS
= 1 (DS21Q41 emulation). This signal is not bonded out in the DS21FF42/DS21FT42.
Signal Name:
TCHBLK
Signal Description:
Transmit Channel Block
Signal Type:
Output
A user programmable output that can be forced high or low during any of the 24 T1 channels.
Synchronous with TCLK when the transmit side elastic store is disabled. Synchronous with TSYSCLK
when the transmit side elastic store is enabled. Useful for blocking clocks to a serial UART or LAPD
controller in applications where not all T1 channels are used such as Fractional T1, 384 Kbps service,
768 Kbps or ISDN–PRI . Also useful for locating individual channels in drop–and–insert applications,
for external per–channel loopback, and for per–channel conditioning. See Section 16 for details. This
signal is not bonded out in the DS21FF42/DS21FT42.
Signal Name:
TSYSCLK
Signal Description:
Transmit System Clock
Signal Type:
Input
1.544 MHz or 2.048 MHz clock. Only used when the transmit side elastic store function is enabled.
Should be tied low in applications that do not use the transmit side elastic store. Can be burst at rates up
to 8.192 MHz. This pin is tied to the RSYSCLK signal in the DS21FF42/DS21FT42.
Signal Name:
TLCLK
Signal Description:
Transmit Link Clock
Signal Type:
Output
4 kHz or 2 kHz (ZBTSI) demand clock for the TLINK input. See Section 19 for details. This signal is
not bonded out in the DS21FF42/DS21FT42.
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