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參數(shù)資料
| 型號(hào)： | DS2187 |
| 廠商： | DALLAS SEMICONDUCTOR |
| 元件分類(lèi)： | 數(shù)字傳輸電路 |
| 英文描述： | Receive Line Interface(接收線(xiàn)接口) |
| 中文描述： | DATACOM, PCM TRANSCEIVER, PDIP18 |
| 封裝： | 0.300 INCH, DIP-18 |
| 文件頁(yè)數(shù)： | 2/9頁(yè) |
| 文件大小： | 85K |
| 代理商： | DS2187 |
DS2187
022798 2/9
DS2187 BLOCK DIAGRAM
Figure 1
RAIS
AIS
DATA
SLICER
CLOCK
SLICER
PEAK DETECT
CLOCK EXTRACTION
RCLKSEL
RPOS
RNEG
ZCSEN
BPV
RCL
LOCK
RCLK
RTIP
RRING
DVDD
AVDD
DVSS
AVSS
LCAP
Z
S
A
D
LINE INPUT
Input signals are coupled to the DS2187 via a 1:2 cen-
ter–tapped transformer as shown in Figure 2. For T1
applications, R1 and R2 must be 200 ohms in order to
properly terminate the line at 100 ohms. R1 and R2 are
set at 150 or 240 ohms for CEPT applications. Special
internal circuitry of the RTIP and RRING inputs permits
negative signal excursions below V
SS
, which will occur
in the circuit in Figure 2.
PEAK DETECTOR AND SLICERS
Signal pulses present at RTIP and RRING are sampled
by an internal peak detect circuit. The clock and data
slicer threshold are set for 50% of the sampled peak
voltage.
Peak input levels at RRIP and RRING must exceed 0.6
volts to establish minimum slicer thresholds. Signals
below this level will cause RCL to transition high after
192 bit times.
CLOCK EXTRACTION
The DS2187 utilizes both frequency locked (FLL) and
digital phase locked (DPLL) loops to recover data and
clock from the incoming AMI signal. T1 applications uti-
lize a 18.528 MHz clock divided by either 11, 12, or 13 to
match the phase of the incoming jittered line signal. This
technique affords exceptional jitter tracking which en-
ables the DS2187 to meet the latest AT&T TR 62411
and ECSA jitter specifications. A 24.576 MHz clock di-
vided by 11, 12, or 13 provides jitter tracking in the CEPT
mode. The DPLL output is buffered and presented at
RCLK. An on–chip, laser–trimmed voltage controlled
oscillator (V
CO
) provides the precision 18.528 MHz and
24.576 MHz frequency sources utilized in the FLL. The
FLL is a high–Q circuit which tracks the average fre-
quency of the incoming signal, minimizing the effect of
the DPLL on output jitter.
During the acquisition time or if RCL goes high, the
LOCK pin will go low to indicate a loss of synchroniza-
tion to the line signal. Once this pin goes high, the FLL
has achieved frequency lock and valid data is present at
the RPOS and RNEG outputs.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| DS2187+ | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC Receive Line Interface RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| DS2187S | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC Receive Line Interface RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| DS2187S/T&R | 制造商:Maxim Integrated Products 功能描述:IC RECEIVE LINE INTERFACE 20SOIC |
| DS2187S/T&R | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC Receive Line Interface RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| DS2187S+ | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC Receive Line Interface RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
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