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參數(shù)資料
| 型號(hào)： | DS2186+ |
| 廠商： | Maxim Integrated Products |
| 文件頁(yè)數(shù)： | 6/11頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC TRANSMIT LINE INTERFACE 20DIP |
| 標(biāo)準(zhǔn)包裝： | 18 |
| 類型： | 線路驅(qū)動(dòng)器，發(fā)射器 |
| 驅(qū)動(dòng)器/接收器數(shù)： | 1/0 |
| 規(guī)程： | T1/CEPT |
| 電源電壓： | 4.75 V ~ 5.25 V |
| 安裝類型： | 通孔 |
| 封裝/外殼： | 20-DIP（0.300"，7.62mm） |
| 供應(yīng)商設(shè)備封裝： | 20-PDIP |
| 包裝： | 管件 |
DS2186
022798 4/11
The shape of the “pre–emphasized” T1 waveform is
controlled
by
inputs
LEN0,
LEN1,
and
LEN2
(TCLKSEL=0). These control inputs allow the user to
select the appropriate output pulse shape to meet
DSX–1 or CSU templates over a wide variety of cable
types and lengths. Those cable types include ABAM,
PIC, and PULP.
The CEPT mode is enabled when TCLKSEL=1. Only
one output pulse shape is available in the CEPT mode;
inputs LEN0, LEN1 and LEN2 can be any state except
all zeros.
The line coupling transformer also contributes to the
pulse shape seen at the cross–connect point. Trans-
formers for both T1 and CEPT applications must be
1:1.35.
The wave shaping circuitry does not contribute signifi-
cantly to output jitter (less than 0.01 UIpp broadband).
Output jitter will be dominated by the jitter on TCLK or
LCLK. TCLK and LCLK need only be accurate in fre-
quency, not duty cycle.
LINE DRIVERS
The on–chip differential line drivers interface directly to
the output transformer. To optimize device perform-
ance, length of the TTIP and TRING traces should be
minimized and isolated from neighboring interconnect.
FAULT PROTECTION
The line drivers are fault–protected and will withstand a
shorted transformer secondary (or primary) without
damage. Inputs MTIP and MRING are normally tied to
TTIP and TRING to provide fault monitoring capability.
Output LF will transition low if 192 TCLK cycles occur
without a one occurring at MTIP or MRING. LF will tri–
state on the next one occurrence or two TCLK periods
later, whichever is greater.
The threshold of MTIP and MRING varies with the line
type selected at LEN0, LEN1 and LEN2. This insures
detection of the lowest level zero to one transition (–15
dB buildout) as it occurs on TTIP and TRING.
T1 LINE LENGTH SELECTION Table 2
LEN2
LEN1
LEN0
OPTION SELECTED
APPLICATION
0
Test mode
Do not use
0
1
–7.5 dB buildout
T1 CSU
0
1
0
–15 dB buildout
T1 CSU
0
1
0 dB buildout,
0 – 133 feet
T1 CSU, DSX–1 Cross connect
1
0
133 – 266 feet
DSX–1 Cross connect
1
0
1
266 – 399 feet
DSX–1 Cross connect
1
0
399 – 533 feet
DSX–1 Cross connect
1
533 – 655 feet
DSX–1 Cross connect
NOTE:
1. The LEN0, LEN1 and LEN2 inputs control T1 output waveshapes when TCLKSEL=0. The G.703 (CEPT) template
is selected when TCLKSEL=1 and LEN0, LEN1, and LEN2 are at any state except all zeros.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| DS2186+ | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC Transmit Line Interface RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| DS2186N | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:CEPT/T1 Interface |
| DS2186S | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| DS2186S/T&R | 制造商:Maxim Integrated Products 功能描述:TRANSMIT LINE INTERFACE SOIC TRL - Tape and Reel 制造商:Maxim Integrated Products 功能描述:IC TRANSMIT LINE INTERFC 20-SOIC |
| DS2186S/T&R | 功能描述:IC TRANSMIT LINE INTERFC 20-SOIC RoHS:否 類別:集成電路 (IC) >> 接口 - 驅(qū)動(dòng)器，接收器，收發(fā)器 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:25 系列:- 類型:收發(fā)器 驅(qū)動(dòng)器/接收器數(shù):2/2 規(guī)程:RS232 電源電壓:4.5 V ~ 5.5 V 安裝類型:通孔 封裝/外殼:16-DIP（0.300"，7.62mm） 供應(yīng)商設(shè)備封裝:16-PDIP 包裝:管件 |
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