參數(shù)資料
型號(hào): DS2180AQN+
廠商: Maxim Integrated Products
文件頁數(shù): 13/35頁
文件大?。?/td> 0K
描述: IC TRANSCEIVER T1 IND 44-PLCC
產(chǎn)品培訓(xùn)模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝: 28
功能: 收發(fā)器
接口: T1
電路數(shù): 1
電源電壓: 4.5 V ~ 5.5 V
電流 - 電源: 3mA
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 44-LCC(J 形引線)
供應(yīng)商設(shè)備封裝: 44-PLCC(16.59x16.59)
包裝: 管件
包括: 警報(bào)生成和檢測(cè),B7 填充模式,B8ZS 模式,錯(cuò)誤檢測(cè)和計(jì)數(shù)器,“硬件”模式,透明模式
產(chǎn)品目錄頁面: 1429 (CN2011-ZH PDF)
DS2180A
20 of 35
BVCR: BIPOLAR VIOLATION COUNT REGISTER Figure 19
(MSB)
(LSB)
BVD7
BVD6
BVD5
BVD4
BVD3
BVD2
BVD1
BVD0
SYMBOL
POSITION
NAME AND DESCRIPTION
BVD7
BVCR.7
MSB of bipolar count.
BDV0
BVCR.0
LSB of bipolar count.
This 8-bit binary up counter saturates at 255 and will generate an interrupt for each occurrence of a
bipolar violation once saturated (RIMR.7=1). Presetting this register allows the user to establish specific
count interrupt thresholds. The counter will count “up” to saturation from the preset valued and may be
read at any time. Counter increments occur at all times and are not disabled by resync. If B8ZS is enabled
(CCR.2=1) bipolar violations are not counted for B8ZS code words.
ECR: ERROR COUNT REGISTER Figure 20
(MSB)
(LSB)
OOFD3
OOFD2
OOFD1
OOFD0
ESFD3
ESFD2
ESFD1
ESFD0
ERROR COUNT
ESF ERROR COUNT
SYMBOL
POSITION
NAME AND DESCRIPTION
OOFD3
ECR.7
MSB of OOF event count.
OOFD0
ECR.4
LSB of OOF event count.
ESDF3
ECR.3
MSB of extended superframe error count.
ESFD0
ECR.0
LSB of extended superframe error count.
These separate 4-bit binary up counters saturate at a count of 15 and will generate an interrupt for each
occurrence of an OOF event or an ESF error event after saturation (RIMR.6=1). Presetting these counters
allows the user to establish specific count interrupt thresholds. The counters will count “up” to saturation
from the preset value and may be read at any time. These counters share the same register address and
must be written to or read from simultaneously.
The OOF counter records out-of-frame events in both 193S and 193E. The ESF error counter records
errored superframes in 193E. In 193S, the ESF counter records individual FT and FS errors when
RCR.3=1; FT errors only when RCR.3=0. ECR counter increments are disabled when resync is in
progress (RLOS high).
ALARM OUTPUTS
The transceiver also provides direct alarm outputs for applications when additional decoding and
demuxing are required to supplement the onboard alarm logic.
RLOS OUTPUT
The receive loss of sync output indicates the status of the receiver synchronizer circuitry; when high, an
off-line resynchronization is in progress and a high-low transition indicates resync is complete. The
RLOS bit (RSR.0) is a “l(fā)atched” version of the RLOS output. If the auto-resync mode is selected
(RCR.1=0), RLOS is a real time indication of a carrier loss or OOF event occurrence.
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