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參數(shù)資料
| 型號： | DS2174QN+T&R |
| 廠商： | Maxim Integrated Products |
| 文件頁數(shù)： | 21/24頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC BERT ENHANCED 44-PLCC |
| 產(chǎn)品培訓(xùn)模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標(biāo)準(zhǔn)包裝： | 500 |
| 功能： | 增強型位誤碼率測試器（EBERT） |
| 接口： | E1，J1，T1 |
| 電路數(shù)： | 1 |
| 電源電壓： | 3 V ~ 3.6 V |
| 電流 - 電源： | 50mA |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 44-LCC（J 形引線） |
| 供應(yīng)商設(shè)備封裝： | 44-PLCC（16.59x16.59） |
| 包裝： | 帶卷 (TR) |
| 包括： | 錯誤計數(shù)器，樣式發(fā)生器和檢測器 |
DS2174
6 of 24
1.5 Clock Discussion
There are two methods for moving test patterns through a telecom network.
1) The clock applied to TCLK and RCLK can be gapped by other devices on the target system. The
gapped clock would be applied to TCLK and RCLK only during the appropriate times. TDATn
outputs remain active during clock gaps.
2) The clock applied to TCLK and RCLK can be continuous at the applicable line rate and the
TCLK_EN and RCLK_EN pins can be asserted and deasserted during the appropriate time slots.
TDATn outputs remain active even when TCLK_EN is pulled low. The output level remains static at
the level of the last bit transmitted (output high for a 1, output low for a 0).
1.6 Power-Up Sequence
On power-up, the registers in the DS2174 are in a random state. The user must program all the internal
registers to a known state before proper operation can be ensured.
Figure 1-1. Block Diagram
BIT COUNTER
ERROR COUNTER
PATTERN DETECTOR
ERROR INSERTION
L
O
PBACK
M
U
X
REPETITIVE PATTERN
GENERATOR
2
n - 1
PARALLEL CONTROL PORT
RECEIVE
RATE
CONTROL
TRANSMIT
RATE
CONTROL
D[7:0]
CS RD WR
A[3:0]
RDAT[7:0]
TCLK0
TDAT[7:0]
TCLK
TCLK_EN
RCLK_EN
RCLK
SYNC
CR1.5
LC
CR1.0
TL
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| DS2175S/T&R | 制造商:Maxim Integrated Products 功能描述:ELASTIC STORE-SOIC-TRL - Tape and Reel 制造商:Maxim Integrated Products 功能描述:IC ELASTIC STORE T1/CEPT 16-SOIC 制造商:Maxim Integrated Products 功能描述:Network Controller & Processor ICs T1/CEPT Elastic Store |
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