參數資料
型號： DS21554L
廠商： Maxim Integrated Products
文件頁數： 117/124頁
文件大?。?/td> 0K
描述： IC TXRX E1 1-CHIP 5V 100-LQFP
產品培訓模塊： Lead (SnPb) Finish for COTS
產品變化通告： Product Discontinuation 20/Feb/2012
標準包裝： 90
功能： 單芯片收發(fā)器
接口： E1，HDLC，J1，T1
電路數： 1
電源電壓： 4.75 V ~ 5.25 V
電流 - 電源： 75mA
工作溫度： 0°C ~ 70°C
安裝類型： 表面貼裝
封裝/外殼： 100-LQFP
供應商設備封裝： 100-LQFP（14x14）
包裝： 托盤
包括： 遠程和 AIS 警報檢測器 / 發(fā)生器
DS21354/DS21554 3.3V/5V E1 Single-Chip Transceivers
92 of 124
TAP Controller State Machine
The TAP controller is a finite state machine that responds to the logic level at JTMS on the rising edge of
JTCLK. See Figure 16-2.
Test-Logic-Reset
Upon power up, the TAP Controller will be in the Test-Logic-Reset state. The Instruction register will
contain the IDCODE instruction. All system logic of the device will operate normally.
Run-Test-Idle
The Run-Test-Idle is used between scan operations or during specific tests. The Instruction register and
test registers will remain idle.
Select-DR-Scan
All test registers retain their previous state. With JTMS LOW, a rising edge of JTCLK moves the
controller into the Capture-DR state and will initiate a scan sequence. JTMS HIGH during a rising edge
on JTCLK moves the controller to the Select-IR-Scan state.
Capture-DR
Data may be parallel-loaded into the test data registers selected by the current instruction. If the
instruction does not call for a parallel load or the selected register does not allow parallel loads, the test
register will remain at its current value. On the rising edge of JTCLK, the controller will go to the Shift-
DR state if JTMS is LOW or it will go to the Exit1-DR state if JTMS is HIGH.
Shift-DR
The test data register selected by the current instruction will be connected between JTDI and JTDO and
will shift data one stage towards its serial output on each rising edge of JTCLK. If a test register selected
by the current instruction is not placed in the serial path, it will maintain its previous state.
Exit1-DR
While in this state, a rising edge on JTCLK will put the controller in the Update-DR state, which
terminates the scanning process, if JTMS is HIGH. A rising edge on JTCLK with JTMS LOW will put
the controller in the Pause-DR state.
Pause-DR
Shifting of the test registers is halted while in this state. All test registers selected by the current
instruction will retain their previous state. The controller will remain in this state while JTMS is LOW. A
rising edge on JTCLK with JTMS HIGH will put the controller in the Exit2-DR state.
Exit2-DR
A rising edge on JTCLK with JTMS HIGH while in this state will put the controller in the Update-DR
state and terminate the scanning process. A rising edge on JTCLK with JTMS LOW will enter the Shift-
DR state.
Update-DR
A falling edge on JTCLK while in the Update-DR state will latch the data from the shift register path of
the test registers into the data output latches. This prevents changes at the parallel output due to changes
in the shift register.
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相關代理商/技術參數
參數描述
DS21554L+ 功能描述:網絡控制器與處理器 IC 3.3/5V E1 Transceiver RoHS:否 制造商:Micrel 產品:Controller Area Network (CAN) 收發(fā)器數量: 數據速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray
DS21554LB 功能描述:網絡控制器與處理器 IC 3.3/5V E1 Transceiver RoHS:否 制造商:Micrel 產品:Controller Area Network (CAN) 收發(fā)器數量: 數據速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray
DS21554LB+ 功能描述:網絡控制器與處理器 IC 3.3/5V E1 Transceiver RoHS:否 制造商:Micrel 產品:Controller Area Network (CAN) 收發(fā)器數量: 數據速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray
DS21554LBN 功能描述:網絡控制器與處理器 IC RoHS:否 制造商:Micrel 產品:Controller Area Network (CAN) 收發(fā)器數量: 數據速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray
DS21554LBN+ 功能描述:網絡控制器與處理器 IC 3.3/5V E1 Transceiver RoHS:否 制造商:Micrel 產品:Controller Area Network (CAN) 收發(fā)器數量: 數據速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray
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