參數(shù)資料
型號(hào): DS2151QN
廠商: Maxim Integrated Products
文件頁(yè)數(shù): 16/60頁(yè)
文件大?。?/td> 0K
描述: IC TXRX T1 1-CH 5V LP IND 44PLCC
標(biāo)準(zhǔn)包裝: 1
功能: 單芯片收發(fā)器
接口: T1
電路數(shù): 1
電源電壓: 4.75 V ~ 5.25 V
電流 - 電源: 65mA
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 44-LCC(J 形引線)
供應(yīng)商設(shè)備封裝: 44-PLCC(16.59x16.59)
包裝: 管件
包括: 警報(bào)檢測(cè)器和發(fā)生器,CSU 回路代碼發(fā)生器和檢測(cè)器,DSX-1和CSU 線路補(bǔ)償發(fā)生器
DS2151Q
23 of 60
Table 5-2. Alarm Set and Clear Criteria
ALARM
SET CRITERIA
CLEAR CRITERIA
Blue Alarm (AIS) (see note below)
When over a 3ms window, five or
less 0s are received
When over a 3ms window, six or
more 0s are received
Yellow Alarm
1. D4 bit 2 mode (RCR2.2=0)
2. D4 12th F-bit mode (RCR2.2=1;
this mode is also referred to as
the “Japanese Yellow Alarm”)
3. ESF Mode
When bit 2 of 256 consecutive
channels is set to 0 for at least 254
occurrences
When the 12th framing bit is set to
1 for two consecutive occurrences
When 16 consecutive patterns of
00FF hex appear in the FDL
When bit 2 of 256 consecutive
channels is set to 0 for less than 254
occurrences
When the 12th framing bit is set to 0
for two consecutive occurrences
When 14 or less patterns of 00FF
hex out of 16 possible appear in the
FDL
Red Alarm (RCL) (this alarm is
also referred to as Loss of Signal)
When 192 consecutive 0s are
received
When 14 or more 1s out of 112
possible bit positions are received
starting with the first 1 received
Note: The definition of Blue Alarm (or Alarm Indication Signal) is an unframed all-ones signal. Blue alarm detectors should
be able to operate properly in the presence of a 10-3 error rate and they should not falsely trigger on a framed all-ones signal.
The blue alarm criteria in the DS2151Q has been set to achieve this performance. It is recommended that the RBL bit be
qualified with the RLOS status bit in detecting a blue alarm.
5.1
Loop Up/Down Code Detection
Bits SR1.7 and SR1.6 will indicate when either the standard Loop Up or Loop Down codes are being
received by the DS2151Q. When a Loop Up code has been received for 5 seconds, the CPE is expected to
loop the recovered data (without correcting BPVs) back to the source. The Loop Down code indicates
that the loopback should be discontinued. See the AT&T publication TR 62411 for more details. The
DS2151Q will detect the Loop Up/Down codes in both framed and unframed circumstances with bit error
rates as high as 10**-2. The loop code detector has a nominal integration period of 48ms. Hence, after
about 48ms of receiving either code, the proper status bit will be set to a 1. After this initial indication, it
is recommended that the software poll the DS2151Q every 100ms to 500ms until 5 seconds have elapsed
to insure that the code is continuously present. Once 5 seconds have passed, the DS2151Q should be
taken into or out of loopback via the Remote Loopback (RLB) bit in CCR1.
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