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參數(shù)資料
| 型號(hào)： | DS2148T |
| 英文描述： | 5V E1/T1/J1 Line Interface |
| 中文描述： | 5V的E1/T1/J1線路接口 |
| 文件頁數(shù)： | 11/75頁 |
| 文件大?。?/td> | 544K |
| 代理商： | DS2148T |
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DS2148/Q48
11 of 75
PIN DESCRIPTIONS IN PARALLEL PORT MODE
(Sorted by Pin Name,
DS2148T Pin Numbering) Table 4-2b
ACRONYM
PIN
I/O
DESCRIPTION
A0
To
A4
7
0, BIS0 = 0), these pins are not used and should be tied low.
ALE
(AS)
port (BIS1 = 0) in multiplexed bus mode (BIS0 = 0), serves to
demultiplex the bus on a positive-going edge. In nonmultiplexed bus
mode (BIS0 = 1), should be tied low.
BIS0/
BIS1
33
See Table 4-1 for details.
BPCLK
31
O
Back Plane Clock.
A 16.384MHz, 8.192MHz, 4.096MHz, or
2.048MHz clock output that is referenced to RCLK selectable via
CCR5.7 and CCR5.6. In hardware mode, defaults to 16.384MHz
output.
CS*
1
I
Chip Select.
Must be low to read or write to the device. CS* is an
active low signal.
D0 / AD0
To
D7 / AD7
12
operation (BIS1 = 0, BIS0 = 0), serves as an 8-bit multiplexed
address/data bus.
HRST*
29
I
Hardware Reset.
Bringing HRST* low will reset the DS2148
setting all control bits to their default state of all zeros.
INT*
23
O
Interrupt [INT*] pin 23.
Flags host controller during conditions
and change of conditions defined in the Status Register. Active low,
open drain output.
MCLK
30
I
Master Clock.
A 2.048MHz (±50ppm) clock source with TTL
levels is applied at this pin. This clock is used internally for both
clock/data recovery and for jitter attenuation. Use of a T1 1.544MHz
clock source is optional.
See Note 1 on clock accuracy at the end of this table.
NA
-
I
Not Assigned.
Should be tied low.
PBEO
24
O
PRBS Bit Error Output.
The receiver will constantly search for a
2
15
-1 or a 2
20
-1 PRBS depending on the ETS bit setting (CCR1.7).
Remains high if out of synchronization with the PRBS pattern. Goes
low when synchronized to the PRBS pattern. Any errors in the
received pattern after synchronization will cause a positive going
pulse (with same period as E1 or T1 clock) synchronous with
RCLK. PRBS bit errors can also be reported to the ECR1 and ECR2
registers by setting CCR6.2 to a logic 1.
PBTS
44
I
Parallel Bus Type Select.
When using the parallel port (BIS1 = 0),
set high to select Motorola bus timing, set low to select Intel bus
timing. This pin controls the function of the RD*(DS*), ALE(AS),
and WR*(R/W*) pins. If PBTS = 1 and BIS1 = 0, then these pins
assume the Motorola function listed in parenthesis (). In serial port
mode, this pin should be tied low.
11
to
I
Address Bus.
In nonmultiplexed bus operation (BIS1 = 0, BIS0 =
1), serves as the address bus. In multiplexed bus operation (BIS1 =
4
I
Address Latch Enable (Address Strobe).
When using the parallel
32/
I
Bus Interface Select Bits 0 & 1.
Used to select bus interface option.
19
to
I/O
Data Bus/Address/Data Bus.
In non-multiplexed bus operation
(BIS1 = 0, BIS0 = 1), serves as the data bus. In multiplexed bus
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| DS2148T+ | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC 5V E1/T1/J1 Line Interface RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| DS2148TA2 | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC 5V E1/T1/J1 Line Interface RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| DS2148TB | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| DS2148TC1 | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| DS2148TN | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC 5V E1/T1/J1 Line Interface RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
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