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參數(shù)資料
| 型號(hào)： | DS21455N+ |
| 廠商： | Maxim Integrated Products |
| 文件頁(yè)數(shù)： | 264/269頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC LIU QUAD T1/E1/J1 256-BGA |
| 產(chǎn)品培訓(xùn)模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標(biāo)準(zhǔn)包裝： | 40 |
| 類型： | 線路接口裝置（LIU） |
| 驅(qū)動(dòng)器/接收器數(shù)： | 4/4 |
| 規(guī)程： | T1/E1/J1 |
| 電源電壓： | 3.135 V ~ 3.465 V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 256-BBGA |
| 供應(yīng)商設(shè)備封裝： | 256-BGA（27x27） |
| 包裝： | 管件 |
| 產(chǎn)品目錄頁(yè)面： | 1430 (CN2011-ZH PDF) |
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DS21455/DS21458 Quad T1/E1/J1 Transceivers
94 of 269
17.1.1 Processor-Based Receive Signaling
The robbed-bit signaling (T1) or TS16 CAS signaling (E1) is sampled in the receive data stream and
copied into the receive signaling registers, RS1 through RS16. In T1 mode, only RS1 through RS12 are
used. The signaling information in these registers is always updated on multiframe boundaries. This
function is always enabled.
17.1.1.1 Change Of State
In order to avoid constant monitoring of the receive signaling registers, the DS21455/DS21458 can be
programmed to alert the host when any specific channel or channels undergo a change of their signaling
state. RSCSE1 through RSCSE4 for E1 and RSCSE1 through RSCSE3 for T1 are used to select which
channels can cause a change of state indication. The change of state is indicated in Status Register 5
(SR1.5). If signaling integration, CCR1.5, is enabled then the new signaling state must be constant for
three multiframes before a change of state indication is indicated. The user can enable the INT pin to
toggle low upon detection of a change in signaling by setting the IMR1.5 bit. The signaling integration
mode is global and cannot be enabled on a channel-by-channel basis.
The user can identity which channels have undergone a signaling change of state by reading the
RSINFO1 through RSINFO4 registers. The information from this registers will tell the user which RSx
register to read for the new signaling data. All changes are indicated in the RSINFO1–RSINFO4 register
regardless of the RSCSE1–RSCSE4 registers.
17.1.2 Hardware-Based Receive Signaling
In hardware-based signaling the signaling data can be obtained from the RSER pin or the RSIG pin.
RSIG is a signaling PCM-stream output on a channel-by-channel basis from the signaling buffer. The
signaling data, T1 robbed bit or E1 TS16, is still present in the original data stream at RSER. The
signaling buffer provides signaling data to the RSIG pin and also allows signaling data to be reinserted
into the original data stream in a different alignment that is determined by a multiframe signal from the
RSYNC pin. In this mode, the receive elastic store can be enabled or disabled. If the receive elastic store
is enabled, then the backplane clock (RSYSCLK) can be either 1.544MHz or 2.048MHz. In the ESF
framing mode, the ABCD signaling bits are output on RSIG in the lower nibble of each channel. The
RSIG data is updated once a multiframe (3ms) unless a freeze is in effect. In the D4 framing mode, the
AB signaling bits are output twice on RSIG in the lower nibble of each channel. Hence, bits 5 and 6
contain the same data as bits 7 and 8 respectively in each channel. The RSIG data is updated once a
multiframe (1.5ms) unless a freeze is in effect. See the Functional Timing Diagrams for some examples.
17.1.2.1 Receive-Signaling Reinsertion at RSER
In this mode, the user will provide a multiframe sync at the RSYNC pin and the signaling data will be
reinserted based on this alignment. In T1 mode, this results in two copies of the signaling data in the
RSER data stream. The original signaling data based on the Fs/ESF frame positions and the realigned
data based on the user supplied multiframe sync applied at RSYNC. In voice channels this extra copy of
signaling data is of little consequence. Reinsertion can be avoided in data channels since this feature is
activated on a per-channel basis. For reinsertion, the elastic store must be enabled; however, the
backplane clock can be either 1.544MHz or 2.048MHz.
Signaling reinsertion mode is enabled, on a per-channel basis by setting the RSRCS bit high in the PCPR
register. The channels that are to have signaling reinserted are selected by writing to the PCDR1-PCDR3
registers for T1 mode and PCDR1–PCDR4 registers for E1 mode. In E1 mode, the user will generally
select all channels when doing reinsertion.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| DS2148GN+ | IC LIU E1/T1/J1 3.3V/5V 49-BGA |
| DS2148T | IC LIU E1/T1/J1 5V 44-TQFP |
| DS2149Q+ | IC LIU T1/J1 5V 28-PLCC |
| DS2151QN | IC TXRX T1 1-CH 5V LP IND 44PLCC |
| DS2152L+ | IC TXRX T1 1CHIP ENHNCD 100-LQFP |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| DS21455N+ | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC Quad E1-T1-J1 Transceiver RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| DS21458 | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC Quad E1-T1-J1 Transceiver RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| DS21458+ | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC Quad E1-T1-J1 Transceiver RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| DS21458DK | 功能描述:網(wǎng)絡(luò)開發(fā)工具 DS21458 Dev Kit RoHS:否 制造商:Rabbit Semiconductor 產(chǎn)品:Development Kits 類型:Ethernet to Wi-Fi Bridges 工具用于評(píng)估:RCM6600W 數(shù)據(jù)速率:20 Mbps, 40 Mbps 接口類型:802.11 b/g, Ethernet 工作電源電壓:3.3 V |
| DS21458LDK | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
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