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參數資料
| 型號： | DS2143Q+ |
| 廠商： | Maxim Integrated Products |
| 文件頁數： | 6/44頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC CONTROLLER E1 5V LP 44-PLCC |
| 產品培訓模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標準包裝： | 26 |
| 控制器類型： | E1 控制器 |
| 接口： | 并行/串行 |
| 電源電壓： | 4.5 V ~ 5.5 V |
| 電流 - 電源： | 10mA |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 44-LCC（J 形引線） |
| 供應商設備封裝： | 44-PLCC（16.59x16.59） |
| 包裝： | 管件 |
| 產品目錄頁面： | 1429 (CN2011-ZH PDF) |
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DS2143/DS2143Q
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4.0 STATUS AND INFORMATION REGISTERS
There is a set of four registers that contain information on the current real time status of the DS2143:
Status Register 1 (SR1), Status Register 2 (SR2), Receive Information Register (RIR), and Synchronizer
Status Register (SSR). When a particular event has occurred (or is occurring), the appropriate bit in one
of these three registers will be set to a 1. All of the bits in these registers operate in a latched fashion
(except for the SSR). This means that if an event occurs and a bit is set to a 1 in any of the registers, it
will remain set until the user reads that bit. The bit will be cleared when it is read and it will not be set
again until the event has occurred again or if the alarm(s) is still present.
The user will always precede a read of the SR1, SR2, and RIR registers with a write. The byte written to
the register will inform the DS2143 which bits the user wishes to read and have cleared. The user will
write a byte to one of these three registers, with a 1 in the bit positions he or she wishes to read and a 0 in
the bit positions he or she does not wish to obtain the latest information on. When a 1 is written to a bit
location, the read register will be updated with current value and it will be cleared. When a 0 is written to
a bit position, the read register will not be updated and the previous value will be held. A write to the
status and information registers will be immediately followed by a read of the same register. The read
result should be logically AND’ed with the mask byte that was just written and this value should be
written back into the same register to insure that the bit does indeed clear. This second write is necessary
because the alarms and events in the status registers occur asynchronously in respect to their access via
the parallel port. This scheme allows an external microcontroller or microprocessor to individually poll
certain bits without disturbing the other bits in the register. This operation is key in controlling the
DS2143 with higher order software languages.
The SSR register operates differently than the other three. It is a read only register and it reports the status
of the synchronizer in real time. This register is not latched and it is not necessary to precede a read of
this register with a write.
The SR1 and SR2 registers have the unique ability to initiate a hardware interrupt via the INT1 and INT2
pins respectively. Each of the alarms and events in the SR1 and SR2 can be either masked or unmasked
from the interrupt pins via the Interrupt Mask Register 1 (IMR1) and Interrupt Mask Register 2 (IMR2)
respectively.
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相關代理商/技術參數 |
參數描述 |
|---|---|
| DS2143Q/T&R | 制造商:Maxim Integrated Products 功能描述:IC CONTROLLER E1 5V LP 44-PLCC 制造商:Maxim Integrated Products 功能描述:Network Controller & Processor ICs E1 Controller w/Elastic Store |
| DS2143Q/T&R | 功能描述:網絡控制器與處理器 IC E1 Controller w/Elastic Store RoHS:否 制造商:Micrel 產品:Controller Area Network (CAN) 收發(fā)器數量: 數據速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| DS2143Q+ | 功能描述:網絡控制器與處理器 IC E1 Controller w/Elastic Store RoHS:否 制造商:Micrel 產品:Controller Area Network (CAN) 收發(fā)器數量: 數據速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| DS2143QN | 功能描述:網絡控制器與處理器 IC E1 Controller w/Elastic Store RoHS:否 制造商:Micrel 產品:Controller Area Network (CAN) 收發(fā)器數量: 數據速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| DS2143QN/T&R | 制造商:Rochester Electronics LLC 功能描述: 制造商:Maxim Integrated Products 功能描述:IC CONTROLLER E1 5V LP 44-PLCC |
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