參數(shù)資料
型號(hào): DS21372TN+
廠商: Maxim Integrated Products
文件頁(yè)數(shù): 4/22頁(yè)
文件大?。?/td> 0K
描述: IC TESTER BIT ERROR 3.3V 32-TQFP
產(chǎn)品培訓(xùn)模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝: 250
功能: 位誤碼率測(cè)試器(BERT)
接口: T1
電路數(shù): 1
電源電壓: 3 V ~ 3.6 V
電流 - 電源: 10mA
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 32-TQFP
供應(yīng)商設(shè)備封裝: 32-TQFP(7x7)
包裝: 托盤
包括: 錯(cuò)誤計(jì)數(shù)器,樣式發(fā)生器和檢測(cè)器
DS21372
12 of 22
BIT COUNT REGISTERS
(MSB)
(LSB)
BC31
BC30
BC29
BC28
BC27
BC26
BC25
BC24
BCR3 (addr.=08 Hex)
BC23
BC22
BC21
BC20
BC19
BC18
BC17
BC16
BCR2 (addr.=09 Hex)
BC15
BC14
BC13
BC12
BC11
BC10
BC9
BC8
BCR1 (addr.=0A Hex)
BC7
BC6
BC5
BC4
BC3
BC2
BC1
BC0
BCR0 (addr.=0B Hex)
9. BIT ERROR COUNT REGISTERS
The Bit Error Count Registers (BECR3 to BECR0) comprise a 32-bit count of bits received in error at
RDATA. The bit error counter is disabled during loss of SYNC. BEC31 is the MSB of the 32-bit count.
The Status Register bit BECOF is set when this 32-bit register overflows. Upon an overflow condition,
the user must clear the BECR by either toggling the LC bit or pin. The DS21372 latches the bit error
count into the BECR registers and clears the internal bit error count when either the PCR.4 bit or the LC
input pin toggles from low to high. The bit count (available via the BCRs) and bit error count are used by
an external processor to compute the BER performance on a loop or channel basis.
BIT ERROR COUNT REGISTERS
(MSB)
(LSB)
BEC31
BEC30
BEC29
BEC28
BEC27
BEC26
BEC25
BEC24
BECR3 (addr.=0C Hex)
BEC23
BEC22
BEC21
BEC20
BEC19
BEC18
BEC17
BEC16
BECR2 (addr.=0D Hex)
BEC15
BEC14
BEC13
BEC12
BEC11
BEC10
BEC9
BEC8
BECR1 (addr.=0E Hex)
BEC7
BEC6
BEC5
BEC4
BEC3
BEC2
BEC1
BEC0
BECR0 (addr.=0F Hex)
10. PATTERN RECEIVE REGISTERS
The Pattern Receive Register (PRR) provides access to the data patterns received at RDATA. The
operation of these registers depends on the synchronization status of the DS21372. Asserting the RL bit
(PCR.3) or pin during an out-of -sync condition (SR.0 = 0) will latch the previous 32 bits of data received
at RDATA into the PRR registers. When the DS21372 is in sync (SR.0 = 1) asserting RL will latch the
pattern that to which the device has established synchronization. Since the receiver has no knowledge of
the start or end of the pattern, the data in the PRR registers will have no particular alignment. As an
example, if the receiver has synchronized to the pattern 00100110, PRR1 may report 10011000,
11000100 or any rotation thereof. Once synchronization is established, bit errors cannot be viewed in the
PRR registers.
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