參數(shù)資料
型號(hào): DS21348TN
廠商: Maxim Integrated Products
文件頁(yè)數(shù): 22/76頁(yè)
文件大?。?/td> 0K
描述: IC LIU LN T1/E1/J1 3.3V 44-TQFP
產(chǎn)品培訓(xùn)模塊: Lead (SnPb) Finish for COTS
產(chǎn)品變化通告: Product Discontinuation 20/Feb/2012
標(biāo)準(zhǔn)包裝: 160
類型: 線路接口裝置(LIU)
驅(qū)動(dòng)器/接收器數(shù): 1/1
規(guī)程: T1/E1/J1
電源電壓: 3.135 V ~ 3.465 V
安裝類型: 表面貼裝
封裝/外殼: 44-TQFP
供應(yīng)商設(shè)備封裝: 44-TQFP(10x10)
包裝: 托盤
DS21348/DS21Q348
29 of 76
4. CONTROL REGISTERS
CCR1 (00H): COMMON CONTROL REGISTER 1
(MSB)
(LSB)
ETS
NRZE
RCLA
ECUE
JAMUX
TTOJ
TTOR
LOTCMC
SYMBOL
POSITION
DESCRIPTION
ETS
CCR1.7
E1/T1 Select.
0 = E1
1 = T1
NRZE
CCR1.6
NRZ Enable.
0 = Bipolar data at RPOS/RNEG and TPOS/TNEG
1 = NRZ data at RPOS and TPOS or TNEG; RNEG outputs a positive
going pulse when device receives a BPV, CV, or EXZ. See Figure 1-2
RCLA
CCR1.5
Receive Carrier Loss Alternate Criteria.
0 = RCL declared upon 255 (E1) or 192 (T1) consecutive zeros
1 = RCL declared upon 2048 (E1) or 1544 (T1) consecutive zeros
ECUE
CCR1.4
Error Counter Update Enable. A 0 to 1 transition forces the next clock
cycle to load the error counter registers with the latest counts and reset
the counters. The user must wait a minimum of two clocks cycles (976ns
for E1 and 1296ns for T1) before reading the error count registers to
allow for a proper update. See Section 4 and Figure 1-2 for details.
JAMUX
CCR1.3
Jitter Attenuator MUX. Controls the source for JACLK (Figure 1-1).
0 = JACLK sourced from MCLK (2.048MHz or 1.544MHz at MCLK)
1 = JACLK sourced from internal PLL (2.048MHz at MCLK)
TTOJ
CCR1.2
TCLK to JACLK. Internally connects TCLK to JACLK (Figure 1-3).
0 = disabled
1 = enabled
TTOR
CCR1.1
TCLK to RCLK. Internally connects TCLK to RCLK (Figure 1-3).
0 = disabled
1 = enabled
LOTCMC
CCR1.0
Loss Of Transmit Clock Mux Control. Determines whether the
transmit logic should switch to JACLK if the TCLK input should fail to
transition (Figure 1-3).
0 = do not switch to JACLK if TCLK stops
1 = switch to JACLK if TCLK stops
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