參數(shù)資料
型號: DS1994
英文描述: 4kb Plus Time Memory iButton
中文描述: 4K位、帶有時鐘的存儲器iButton®
文件頁數(shù): 14/22頁
文件大?。?/td> 254K
代理商: DS1994
DS1994
Figure 8. HARDWARE CONFIGURATION
14 of 22
Open Drain
Port Pin
RX = RECEIVE
TX = TRANSMIT
100
MOSFET
V
PUP
RX
TX
TX
RX
DATA
R
PU
5 μA
Typ.
BUS MASTER
DS1994 1-Wire PORT
TRANSACTION SEQUENCE
The protocol for accessing the DS1994 through the 1-Wire port is as follows:
Initialization
ROM Function Command
Memory Function Command
Transaction/Data
INITIALIZATION
All transactions on the 1-Wire bus begin with an initialization sequence. The initialization sequence
consists of a reset pulse transmitted by the bus master, followed by presence pulse(s) transmitted by the
slave(s). The presence pulse lets the bus master know that the DS1994 is on the bus and is ready to
operate. For more details, see the
1-Wire Signaling
section.
ROM FUNCTION COMMANDS
Once the bus master has detected a presence, it can issue one of the four ROM function commands. All
ROM function commands are 8 bits long. A list of these commands follows (see the flowchart in Figure
9).
Read ROM [33h]
This command allows the bus master to read the DS1994’s 8-bit family code, unique 48-bit serial num-
ber, and 8-bit CRC. This command can only be used if there is a single DS1994 on the bus. If more than
one slave is present on the bus, a data collision occurs when all slaves try to transmit at the same time
(open drain produces a wired-AND result). The resultant family code and 48–bit serial number usually
result in a mismatch of the CRC.
Match ROM [55h]
The match ROM command, followed by a 64-bit ROM sequence, allows the bus master to address a
specific DS1994 on a multidrop bus. Only the DS1994 that exactly matches the 64-bit ROM sequence
responds to the subsequent memory function command. All slaves that do not match the 64-bit ROM
sequence wait for a reset pulse. This command can be used with a single or multiple devices on the bus.
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