參數(shù)資料
型號: DS1963
廠商: Maxim Integrated Products, Inc.
英文描述: 4K-Bit Monetary iButton(4K位貨幣按鈕)
中文描述: 4K的位貨幣iButton的(4K的位貨幣按鈕)
文件頁數(shù): 17/22頁
文件大?。?/td> 147K
代理商: DS1963
DS1962/DS1963
020698 17/22
1–WIRE SIGNALING
The DS196X requires strict protocols to insure data
integrity. The protocol consists of four types of signaling
on one line: Reset Sequence with Reset Pulse and
Presence Pulse, Write 0, Write 1 and Read Data. All
these signals except presence pulse are initiated by the
bus master. The DS196X can communicate at two dif-
ferent speeds, regular speed and Overdrive Speed. If
not explicitly set into the Overdrive mode, the DS196X
will communicate at regular speed. While in Overdrive
Mode the fast timing applies to all wave forms.
The initialization sequence required to begin any com-
munication with the DS196X is shown in
Figure 10. A
Reset Pulse followed by a Presence Pulse indicates the
DS196X is ready to send or receive data given the cor-
rect ROM command and memory function command.
The bus master transmits (TX) a reset pulse (t
RSTL
,
minimum 480
μ
s at regular speed, 48
μ
s at Overdrive
Speed). The bus master then releases the line and
goes into receive mode (RX). The 1–Wire bus is pulled
to a high state via the pull–up resistor. After detecting
the rising edge on the data pin, the DS196X waits (t
PDH
,
15–60
μ
s at regular speed, 2–6
μ
s at Overdrive speed)
and then transmits the Presence Pulse (t
PDL
, 60–240
μ
s
at regular speed, 8–24
μ
s at Overdrive Speed).
A Reset Pulse of 480
μ
s or longer will exit the Overdrive
Mode returning the device to regular speed. If the
DS196X is in Overdrive Mode and the Reset Pulse is no
longer than 80
μ
s the device will remain in Overdrive
Mode.
Read/Write Time Slots
The definitions of write and read time slots are illustrated
in Figure 11. All time slots are initiated by the master
driving the data line low. The falling edge of the data line
synchronizes the DS196X to the master by triggering a
delay circuit in the DS196X. During write time slots, the
delay circuit determines when the DS196X will sample
the data line. For a read data time slot, if a “0” is to be
transmitted, the delay circuit determines how long the
DS196X will hold the data line low overriding the 1 gen-
erated by the master. If the data bit is a “1”, the device
will leave the read data time slot unchanged.
INITIALIZATION PROCEDURE “RESET AND PRESENCE PLUSES”
Figure 10
t
RSTH
t
RSTL
t
R
V
V
PULPULLUP
IH MIN
V
IL MAX
Regular Speed
480
μ
s < t
RSTL
<
480
μ
s < t
RSTH
<
15
μ
s < t
PDH
< 60
μ
s
60
μ
s < t
PDL
< 240
μ
s
*
**
t
PDH
t
PDL
MASTER R
X
“PRESENCE PULSE”
MASTER T
X
“RESET PULSE”
RESISTOR
MASTER
DS196X
Overdrive Speed
48
μ
s < t
RSTL
< 80
μ
s
48
μ
s < t
RSTH
<
2
μ
s < t
PDH
< 6
μ
s
8
μ
s < t
PDL
< 24
μ
s
**
*IN ORDER NOT TO MASK INTERRUPT SIGNALING BY OTHER DEVICES ON THE 1–WIRE BUS, t
RSTL
+t
R
SHOULD ALWAYS BE LESS THAN 960
μ
s
**INCLUDES RECOVERY TIME
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