DS1922L/DS1922T
3 of 48
I/O Pin, 1-Wire Read
Read Low Time
(Notes 1, 14)
Read Sample Time
(Notes 1, 14)
Real Time Clock
Standard speed
Overdrive speed
Standard speed
Overdrive speed
5
1
15 -
1.95 -
15
1.95
t
RL
μs
t
RL
+
t
RL
+
t
MSR
μs
Accuracy
+25°C
-2
+2
min/
month
-40°C to +85°C
0°C to +125°C
-300
-600
+60
+60
Frequency Deviation
F
PPM
Temperature Converter
Conversion Time
(Note 15)
Thermal Response Time
Constant (note 16)
Conv. Error Without
Software Correction (note
17)
Conv. Error With Software
Correction (Note 18)
t
CONV
8-bit mode
16-bit mode (11 bits)
30
240
75
600
ms
RESP
iButton package
130
s
See Temperature Accuracy
Graphs
°C
See Temperature Accuracy
Graphs
°C
Note 1:
Note 2:
System Requirement
Maximum allowable pullup resistance is a function of the number of 1-Wire devices in the system and 1-Wire recovery times. The
specified value here applies to systems with only one device and with the minimum 1-Wire recovery times. For more heavily
loaded systems, an active pullup such as that found in the DS2480B may be required.
Capacitance on the data pin could be 800pF when V
PUP
is first applied. If a 2.2k resistor is used to pull up the data line, 2.5μs
after V
PUP
has been applied the parasite capacitance will not affect normal communications.
V
, V
are a function of the internal supply voltage.
Voltage below which, during a falling edge on I/O, a logic '0' is detected.
The voltage on I/O needs to be less or equal to V
ILMAX
whenever the master drives the line low.
Voltage above which, during a rising edge on I/O, a logic '1' is detected.
After V
TH
is crossed during a rising edge on I/O, the voltage on I/O has to drop by V
HY
to be detected as logic '0'.
The I-V characteristic is linear for voltages less than 1V.
The earliest recognition of a negative edge is possible at t
after V
has been previously reached.
Highlighted numbers are NOT in compliance with the published iButton standards. See comparison table below.
Interval during the negative edge on I/O at the beginning of a Presence Detect pulse between the time at which the voltage is
90% of V
PUP
and the time at which the voltage is 10% of V
PUP
.
represents the time required for the pullup circuitry to pull the voltage on I/O up from V
IL
to V
TH
.
represents the time required for the pullup circuitry to pull the voltage on I/O up from V
IL
to the input high threshold of the bus
master.
To conserve battery power, use 8-bit temperature logging whenever possible.
This number was derived from a test conducted by Cemagref in Antony, France, in July of 2000.
http://www.cemagref.fr/English/index.htm
Test Report No. E42.
Includes +0.1/-0.2
C calibration chamber measurement uncertainty.
Assumes using calibration memory with calibration equations for error compensation. Includes +0.1/-0.2
o
C calibration chamber
measurement uncertainty. Guaranteed by design.
Note 3:
Note 4:
Note 5:
Note 6:
Note 7:
Note 8:
Note 9:
Note 10:
Note 11:
Note 12:
Note 13:
Note 14:
Note 15:
Note 16:
Note 17:
Note 18:
STANDARD VALUES
DS1922L/T VALUES
STANDARD SPEED
MIN
61μs
480μs
15μs
60μs
60μs
OVERDRIVE SPEED
MIN
7μs
48μs
2μs
8μs
6μs
STANDARD SPEED
MIN
65μs
1)
690μs
15μs
60μs
60μs
OVERDRIVE SPEED
MIN
9.5μs
70μs
2μs
7μs
7.5μs
PARAMETER
NAME
t
SLOT
(incl. t
REC
)
t
RSTL
t
PDH
t
PDL
t
W0L
1)
Intentional change, longer recovery time requirement due to modified 1-Wire front end.
MAX
(undef.)
(undef.)
60μs
240μs
120μs
MAX
(undef.)
80μs
6μs
24μs
16μs
MAX
(undef.)
720μs
63.5μs
287μs
120μs
MAX
(undef.)
80μs
7μs
28μs
12μs
PHYSICAL SPECIFICATION
Size
Weight
Safety
See mechanical drawing
Ca. 3.3 grams
Meets UL#913 (4
th
Edit.); Intrinsically Safe Apparatus,
approval under Entity Concept for use in Class I,
Division 1, Group A, B, C, and D Locations (application
pending)