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參數(shù)資料
| 型號(hào)： | DS1866Z+T&R |
| 廠商： | Maxim Integrated Products |
| 文件頁(yè)數(shù)： | 2/5頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC POT TRIM LOG 2.7-5.5V 8-SOIC |
| 產(chǎn)品培訓(xùn)模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標(biāo)準(zhǔn)包裝： | 2,500 |
| 接片： | 8 |
| 電阻（歐姆）： | 10k |
| 電路數(shù)： | 1 |
| 溫度系數(shù)： | 標(biāo)準(zhǔn)值 750 ppm/°C |
| 存儲(chǔ)器類型： | 易失 |
| 接口： | 3 輸入并口 |
| 電源電壓： | 2.7 V ~ 5.5 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 8-SOIC（0.154"，3.90mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 8-SOIC |
| 包裝： | 帶卷 (TR) |
DS1866
2 of 5
102199
OPERATION
The DS1866 is a single volatile potentiometer. The device has a total of eight positions providing a
resolution of 5 dB per step and giving a total attenuation range of 0 dB to -35 dB. These tap points are
accessible to the W-terminal whose position is controlled via a 3-terminal parallel port consisting of input
signals P0, P1, and P2. A block diagram of the DS1866 is shown in Figure 1.
Wiper position setting of the DS1866 is determined by the states of the P0, P1, and P2 input terminals.
Table 1 below outlines position setting versus value of the parallel port inputs. A Position-0 setting places
the wiper position at the L-terminal of the potentiometer and provides 35 dB of attenuation. As wiper
position increases, attenuation decreases with Position-7 giving 0 dB of attenuation.
On power-up, the wiper position of the DS1866 will be set to the P0, P1, and P2 values.
P2 P1 P0
(binary)
Wiper
Position
Attenuation
(dB)
000
0
35 dB
001
1
30 dB
010
2
25 dB
011
3
20 dB
100
4
15 dB
101
5
10 dB
110
6
5 dB
111
7
0 dB
PIN DESCRIPTIONS
VCC - Power Supply Terminal. The DS1866 will support supply voltages ranging from +2.7 to +5.5
volts.
GND - Ground Terminal.
H - High-end Resistor. This is the high-end terminal of the potentiometer. It is not required that this
terminal be connected to a potential greater than the L-terminal. Maximum voltage on the H-terminal can
not exceed the power supply voltage, VCC, or go below ground.
L - Low-end Resistor. This is the low-end terminal of the potentiometer. It is not required that this
terminal be connected to a potential less than the H-terminal. Maximum voltage on the L-terminal can not
exceed the power-supply voltage, VCC, or go below ground.
W - Wiper of the Potentiometer. This pin is the wiper terminal of the potentiometer. Its position on the
resistor array is controlled by the 3-terminal parallel port. Maximum voltage on the W-terminal can not
exceed the power supply voltage, VCC, or go below ground.
P0 - Bit 0. P0 is the bit 0 data input to the parallel port.
P1 - Bit 1. P1 is the bit 1 data input to the parallel port.
P2 - Bit 2. P2 is the bit 2 data input to the parallel port.
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